公开(公告)号：EP1290617A4

公开(公告)日：2004-09-29

申请号：EP01935306

申请日：2001-05-10

申请人： CADENCE DESIGN SYSTEMS INC

发明人： FENG DAN ,  PHILLIPS JOEL R ,  KUNDERT KENNETH

IPC分类号： G06F17/50 ,  G06G7/48 ,  G06F7/60

CPC分类号： G06F17/5036

摘要： A process for performing an improved mixed frequency-time algorithm to simulate responses of a circuit that receives a periodic sample signal and at least one information signal, the process selecting a set of evenly spaced distinct time points (804) and a set of reference time points (806). Each of the reference points is associated with a distinct time point, and a reference time point is a signal period away from its respective distinct time point. The process finds a first set of relationships (808) between the values at the distinct time points and the values at the reference time points, and a second set of relationships (810) between the values at the distinct time points and the values at the reference time points. The first and second set of relationships are combined to establish a system of nonlinear equations in terms of the values at the distinct times only (812). The nonlinear equations are solved to find simulated responses of the circuit in the time domain, and the simulated circuit responses are then converted to a frequency domain (814).

公开(公告)号：EP1417607A2

公开(公告)日：2004-05-12

申请号：EP02761174.8

申请日：2002-07-24

申请人： Cadence Design Systems, Inc.

发明人： ELASSAAD, Shauki ,  SALDANHA, Alexander

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/505

摘要： A method/process for repeater insertion in the absence of timing constraints. Delays are optimized for multi-receiver and multi-layer nets (fig.5) and can be introduced in the early steps of design planning. It serves as a tool for interconnect prediction as well as planning. In the presented formulation, no restrictions are made on where the repeaters are added or what the topology of the net is. The tabulated results (page 20) demonstrate improvement (speed ups) using the method/process of the present invention. The present invention runs in linear time and achieves better results that the existing dynamic programming formulation and other published heuristics. Polarity in a circuit design is corrected by traversing the circuit and carrying backwards a cost of fixing the polarity. On a subsequent traversal, buffers inserted fix the polarity (fig. 3).

公开(公告)号：EP1399858A2

公开(公告)日：2004-03-24

申请号：EP01271071.1

申请日：2001-10-19

申请人： Quickturn Design Systems, Inc.

发明人： OHKAMI, Takahide

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A system is prvided to increase the accessibility of registers and memories in a user's design undergoing functional verificationin a hardware-assisted design verification system. A packet-based protocol is used to perform data transfer operations between a host workstation and ahardware accelerator for loading data to and unloading data from the registers and memories in a target design under verification (DUV) during logic simulation. The method and apparatus synthesizes interface logic into the DUV to provide for greater access to the registers and memories in the target DUV which is simulated with the assistance of the hardware accelerator.

公开(公告)号：EP1192559B1

公开(公告)日：2003-10-01

申请号：EP00937633.6

申请日：2000-05-19

申请人： Cadence Design Systems, Inc.

发明人： GINETTI, Arnold

IPC分类号： G06F17/00

CPC分类号： G06F17/505 ,  G06F17/5072

摘要： A method for estimating the position of a matched cell takes into account the interconnective ties of that cell, without relying on the location of cells connected to the matched cell. The new method is referred to as the Weighted Center of Mass of Covered method. In this method, weights are given to the various nodes which are part of the match. These weights are based on the number of connections between the nodes and child nodes of the match. The placement of the matched cell is based on the initial positions given to the nodes making up the match, and the weights calculated for those nodes.

公开(公告)号：EP1314261A2

公开(公告)日：2003-05-28

申请号：EP01959093.4

申请日：2001-07-20

申请人： Cadence Design Systems, Inc.

发明人： GARDNER, Larry ,  VIJ, Vikram ,  GERRARD, Carl A. ,  LI, Bin ,  CHANDER, Sivasankar ,  KUNCHAKARRA, Murthy ,  MCCOY, Timothy, J. ,  SWAN, Richard, Arthur

IPC分类号： H04B3/30

CPC分类号： H04W92/02 ,  H04L12/66 ,  H04W84/12 ,  H04W84/18 ,  H04W88/10

摘要： A Wireless bridge conjoins two previously incompatible technologies within a single device to leverage the strengths of each. The Wireless bridge marries the Personal Area Network (PAN) technology of Bluetooth as described in Bluetooth Specification Version 1.0B with the Wireless Local Area Network (WLAN) technology described in the IEEE802.11a specification to provide a wireless system level solution for peripheral devices to provide Internet service interactions. The invention brings together in a single working device implementations of these technologies so they do not interfere or disrupt the operation of each other and instead provide a seamless transition of a Bluetooth connection to Wireless Local Area Network/Internet connection. From the Wireless Local Area Network perspective the inventive wireless bridge extension allows a Bluetooth-enabled device to roam from one Wireless Access Point (bridge) to the next without losing its back end connection. The invention takes into account the minimum separation and shielding required of these potentially conflicting technologies to inter-operate.

公开(公告)号：EP1303836A1

公开(公告)日：2003-04-23

申请号：EP00920194.8

申请日：2000-04-07

申请人： Cadence Design Systems, Inc.

发明人： Phillips, Joel

IPC分类号： G06N7/08

CPC分类号： G06F17/5036 ,  G06F17/13

摘要： A method and system for generating reduced models of systems having time-varying elements, non-linear elements or both is provided. The system to be modeled is described utilizing differential equations (100). The differential equations of the system are then linearized (110) and the frequency domain representations of the linearized differential equations are obtained (120). A finite dimensional representation of the frequency domain representations is generated (130) and is reduced by Krylov subspace projection (140). The reduced finite dimensional representation is solved (150) to obtain the reduced model of the system.

公开(公告)号：EP1290617A1

公开(公告)日：2003-03-12

申请号：EP01935306.9

申请日：2001-05-10

申请人： Cadence Design Systems, Inc.

发明人： FENG, Dan ,  PHILLIPS, Joel, R. ,  KUNDERT, Kenneth

IPC分类号： G06G7/48 ,  G06F7/60

CPC分类号： G06F17/5036

摘要： A process for performing an improved mixed frequency-time algorithm to simulate responses of a circuit that receives a periodic sample signal and at least one information signal, the process selecting a set of evenly spaced distinct time points (804) and a set of reference time points (806). Each of the reference points is associated with a distinct time point, and a reference time point is a signal period away from its respective distinct time point. The process finds a first set of relationships (808) between the values at the distinct time points and the values at the reference time points, and a second set of relationships (810) between the values at the distinct time points and the values at the reference time points. The first and second set of relationships are combined to establish a system of nonlinear equations in terms of the values at the distinct times only (812). The nonlinear equations are solved to find simulated responses of the circuit in the time domain, and the simulated circuit responses are then converted to a frequency domain (814).

公开(公告)号：EP1145159A3

公开(公告)日：2002-07-10

申请号：EP99954722.7

申请日：1999-09-30

申请人： Cadence Design Systems, Inc.

发明人： CHANG, Henry ,  COOKE, Larry ,  HUNT, Merrill ,  KE, Wuudiann ,  LENNARD, Christopher, K. ,  MARTIN, Grant ,  PATERSON, Peter ,  TRUONG, Khoan ,  VENKATRAMANI, Kumar

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5022 ,  G06F2217/66

公开(公告)号：EP1195004A2

公开(公告)日：2002-04-10

申请号：EP01923205.7

申请日：2001-04-05

申请人： Cadence Design Systems, Inc.

发明人： GRADZKI, Pawel, M.

IPC分类号： H03F1/22

CPC分类号： H03F1/223

摘要： MOS Cascode amplifier circuit including a voltage limiting bias circuit of additional transistors acting as a series voltage-limiting device between the MOS cascode amplifier circuit output node and the drain node of the upper-most cascode connected transistors when the MOS cascode amplifier circuit output voltage is at its maximum value. The drain-source voltage excursion peak on the sensitive cascode transistor is limited to a value below a pre-selected critical voltage, Vcrt. The additional transistors are connected by internal adjacent source-drain nodes as a sequencial chain with gates biased at respective fixed voltages. The number of additional transistors are selected to limit the peak drain-source voltage excursion on the sensitive transistor under operating conditions.

公开(公告)号：EP1177867A3

公开(公告)日：2002-03-06

申请号：EP01122900.2

申请日：1997-03-19

申请人： Design Systems, Inc.

发明人： Rudy, Norman A. ,  Pfarr, Craig E. ,  Wattles, Darren P.

IPC分类号： B26F3/00

CPC分类号： B26F3/004 ,  B26F2003/006 ,  Y10T137/0396 ,  Y10T137/2076 ,  Y10T137/2213 ,  Y10T137/6525

摘要： An apparatus and method for performing high speed interruption of the flow of a very fine, high pressure, high speed water jet 12 of the type used to cut foods, paper and other goods. The water jet 12 is interrupted by a pivotal blocking bar 22 within a blocker housing. The blocking bar 22 is pivoted in a collar 24b to a first desired position out of the path of water jet 12 or to a second desired position for blocking the path of water jet 12. A pivot arm 28, controlled by an output shaft 30 of a rotary actuator 32, controls the rotation of the blocking bar 22. A high pressured airflow is introduced into the device for controlling the exhaustion of blocked water within the device and for cooling the rotary actuator 32.

摘要翻译： 一种用于执行用于切割食物，纸张和其他物品的非常细的高压高速水射流12的流动的高速中断的装置和方法。 水射流12被阻挡器壳体内的枢转阻挡杆22中断。 阻挡杆22在套环24b中枢转到水射流12的路径之外的第一期望位置或第二期望位置以阻挡水射流12的路径。枢转臂28由输出轴30控制， 旋转致动器32控制阻挡杆22的旋转。高压气流被引入到用于控制装置内阻塞的水的消耗并且用于冷却旋转致动器32的装置中。