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232 条记录 (耗时 0.022 秒)

    Dynamic random access memory device
    71.
    发明公开
    Dynamic random access memory device 失效
    动态随机存取存储器

    公开(公告)号：EP0068894A3

    公开(公告)日：1986-02-26

    申请号：EP82303414

    申请日：1982-06-29

    申请人： FUJITSU LIMITED

    发明人： Nakano, Tomio ,  Nakano, Masao ,  Takemae, Yoshihiro ,  Tsuge, Norihisa ,  Ohira, Tsuyoshi

    IPC分类号： G11C11/24

    CPC分类号： G11C11/4099 ,  G06F11/2294

    摘要： A dynamic random access memory device comprises one-transistor, one-capacitor-type memory cells (Coo - C 127.127 ) in rows and columns and dummy cells (DC20'~ DC 2,127 , DC 20 " ~ DC 2.127 ", DC20'" ~ DC 2,127 "') in rows. The capacitors (C d ) of the dummy cells are charged to a high power supply potential (V cc ) by one or more charging transistors (Q A , QA') clocked by a reset clock signal (0R). The capacitors (C d ) of the dummy cells are discharged to a low power supply potential (V ss ) by one or more transistors (Q B , Q B ') clocked by an operation clock signal (⌀ WL ) having a potential lower than the high power supply potential (V cc ).

    Semiconductor memory device
    72.
    发明公开
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：EP0165106A2

    公开(公告)日：1985-12-18

    申请号：EP85400865.3

    申请日：1985-05-03

    申请人： FUJITSU LIMITED

    发明人： Takemae, Yoshihiro ,  Nakano, Tomio ,  Sato, Kimiaki

    IPC分类号： G11C11/407 ,  G11C11/408 ,  G11C11/409

    CPC分类号： G11C8/12 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4097

    摘要： A semiconductor memory device including at least two groups, each of said groups including a plurality of memory cell array blocks (CLAO, CLA1, ...). The number of the memory cell array blocks which are activated in one group is made different from the number of memory cell array blocks which is activated in another group by providing a sequential circuit (S1), thus reducing the maximum power consumption.

    摘要翻译： 一种包括至少两个组的半导体存储器件，每个所述组包括多个存储单元阵列块（CLAO，CLA1，...）。 通过提供时序电路（S1），使在一个组中激活的存储单元阵列块的数量与在另一个组中激活的存储单元阵列块的数量不同，从而降低最大功耗。

    Semiconductor memory device
    73.
    发明公开
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：EP0083229A3

    公开(公告)日：1985-12-04

    申请号：EP82306938

    申请日：1982-12-23

    申请人： FUJITSU LIMITED

    发明人： Takemae, Yoshihiro ,  Nozaki, Shigeki ,  Ohira, Tsuyoshi

    IPC分类号： G11C11/24

    CPC分类号： G11C11/4072

    摘要： A dynamic semiconductor memory device comprises data output lines (D, D), a data output buffer (12), a column enable buffer (9), and an output enable buffer (11) for generating an output enable signal (OE) to enable the transmission of data from the data output lines to the data buffer. The output enable buffer is driven by the clock signals of the column enable buffer. An output disabling circuit (13) is provided so as to stop the generation of an output enable signal by the output enable buffer when the output enable buffer is not being driven by the column enable buffer. As a result, the data output buffer assumes a high-impedance state when a power supply is turned on.

    摘要翻译： 动态半导体存储器件包括用于产生输出使能信号（OE）的数据输出线（D，D），数据输出缓冲器（12），列使能缓冲器（9）和输出使能缓冲器（11） 数据从数据输出线传输到数据缓冲区。 输出使能缓冲器由列使能缓冲器的时钟信号驱动。 提供输出禁止电路（13），以便当输出使能缓冲器未被列使能缓冲器驱动时停止由输出使能缓冲器产生输出使能信号。 结果，当电源接通时，数据输出缓冲器呈现高阻抗状态。

    Dynamic semiconductor memory device
    74.
    发明公开
    Dynamic semiconductor memory device 失效
    动态半导体存储器件

    公开(公告)号：EP0080936A3

    公开(公告)日：1985-11-06

    申请号：EP82402139

    申请日：1982-11-24

    申请人： FUJITSU LIMITED

    发明人： Takemae, Yoshihiro ,  Miyahara, Hatsuo

    IPC分类号： G11C11/24

    CPC分类号： G11C11/4091

    摘要： A dynamic semiconductor memory device includes two bit lines (BL,W connected to a sense amplifier (8) and an active restore circuit (3) which is formed from bit line pull-up transistors (12), each of which is connected between a bit line connected to the sense amplifier and a high potential source. In the active restore circuit, after the sense amplifier is actuated, the bit line pull-up transistor (Q2) connected to the bit line on the high potential side is turn on by supplying a control signal to a gate so that the bit line ( BL ) is pulled up to a high voltage potential. The control signal (Ø2) is maintained at a voltage potential lower than the ground level from the time of actuation of the word line (WLS) to the time of actuation of the sense amplifier (8).

    Semiconductor integrated circuit device having fuse-type information storing circuit
    75.
    发明公开
    Semiconductor integrated circuit device having fuse-type information storing circuit 失效
    Integrierte Halbleiterschaltungsanordnung mit einer Datenspeicherschaltung eines Schmelzsicherungstyps。

    公开(公告)号：EP0159928A2

    公开(公告)日：1985-10-30

    申请号：EP85400552.7

    申请日：1985-03-22

    申请人： FUJITSU LIMITED

    发明人： Takemae, Yoshihiro ,  Nakano, Tomio ,  Tatematsu, Takeo Esuperansa Dai-3 ,  Tsuge, Norihisa ,  Ogawa, Junji ,  Horii, Takashi ,  Fujii, Yasuhiro ,  Nakano, Masao

    IPC分类号： G11C17/00 ,  G06F11/20 ,  G11C8/00

    CPC分类号： G11C29/785 ,  G11C8/10 ,  G11C17/16 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor integrated circuit device connected between first and second voltage feet lines includes an information storing circuit (3) having a fuse (F) for storing information by blowing or not blowing the fuse, a voltage level conversion circuit (10) outputting a voltage (V'cc) lower than a voltage (Vcc) between the first and second voltage feed lines to the information storing circuit, and a circuit (5) connected between the first and second voltage feed lines, for outputting a detection signal (S) in response to a voltage value at the fuse which is varied with the blown or unblown state of the fuse. The output voltage (V'cc) from the voltage level conversion circuit (10) is set as low as possible to restrain electromigration caused atthe vicinity of the blown portion of the fuse, but higher than the threshold voltage of the information detection circuit (5). Said output voltage (V'cc) is at a predetermined value when the voltage between the first and second voltage feed lines is within a predetermined range, and increases in response to the increment of the voltage between the first and second voltage feed lines when said last mentioned voltage exceeds a predetermined range.

    摘要翻译： 连接在第一和第二电压脚线之间的半导体集成电路装置包括：信息存储电路（3），具有用于通过吹送或不熔断熔丝来存储信息的熔丝（F）;输出电压的电压电平转换电路（10） 低于第一和第二电压馈送线之间的电压（Vcc）的信号存储电路;以及电路（5），连接在第一和第二电压馈送线之间，用于输出检测信号 对熔断器的电压值进行响应，该电压值随保险丝的熔断状态或未熔断状态而变化。 来自电压电平转换电路（10）的输出电压（V min cc）被设置为尽可能低以抑制在熔丝的熔断部分附近引起的电迁移但高于信息检测电路（的阈值电压 5）。 当所述第一和第二电压馈电线之间的电压在预定范围内时，所述输出电压（V min cc）为预定值，并且响应于所述第一和第二电压馈电线之间的电压的增加而增加 最后提到的电压超过预定范围。

    Semiconductor memory device
    79.
    发明公开
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：EP0037262A3

    公开(公告)日：1983-06-29

    申请号：EP81301327

    申请日：1981-03-27

    申请人： FUJITSU LIMITED

    发明人： Takemae, Yoshihiro

    IPC分类号： G11C07/00 ,  G11C11/24 ,  H01L27/10

    CPC分类号： G11C11/404 ,  G11C11/4094

    摘要： Each cell (C 00 to C 127 , 127 ) is a one-transistor and one-capacitor type memory cell. Each memory cell (e.g. Coo) is connected to one word line (WLo), to one bit line (BLo) and to one power supply line (WLo). The power supply line WLo is controlled by a gate G'o. The potential of the power supply line WLo can be controlled so as to fall and then rise so as to facilitate the storing of more charges in a capacitor of a memory cell by a boot strap effect.

    Dynamic semiconductor memory
    80.
    发明公开
    Dynamic semiconductor memory 失效
    动态半导体内存

    公开(公告)号：EP0037252A3

    公开(公告)日：1983-06-29

    申请号：EP81301296

    申请日：1981-03-26

    申请人： FUJITSU LIMITED

    发明人： Takemae, Yoshihiro

    IPC分类号： G11C07/00 ,  G11C11/24 ,  G11C08/00

    CPC分类号： G11C11/409 ,  G11C7/00 ,  G11C11/4076 ,  G11C11/408

    摘要： The memory has a plurality of functional blocks such as a row-enable buffer 11, a row-address buffer 12, a word decoder 13, a column-enable buffer 14, a column-address buffer 15, and a column decoder 16. A functional block (e.g. row address buffer 12) is reset by a signal which is provided only when a functional block in a subsequent stage of the memory (e.g. word decoder 13) has begun to operate, and is returned to a state in which it is ready to execute a next processing operation.

    摘要翻译： 存储器具有多个功能块，诸如行启用缓冲器11，行地址缓冲器12，字解码器13，列启用缓冲器14，列地址缓冲器15和列解码器16。 功能块（例如行地址缓冲器12）通过仅在存储器（例如，字解码器13）的后续级中的功能块已经开始操作时才提供的信号而被复位，并且返回到它是 准备好执行下一个处理操作。