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121 条记录 (耗时 0.015 秒)

    Duplicate cache tag memory system
    82.
    发明公开
    Duplicate cache tag memory system 失效
    Anordnung mit Duplikat des Cache-Etikettenspeichers。

    公开(公告)号：EP0681240A2

    公开(公告)日：1995-11-08

    申请号：EP95101636.9

    申请日：1995-02-07

    申请人： Hewlett-Packard Company

    发明人： Hassoun, Joseph H. ,  Ziegler, Michael L. ,  Odineal, Robert D.

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0822

    摘要： An improved memory system for a shared memory multiprocessor computer system in which one or more processor modules and/or input/output modules have cache memories (50, 52, 54). The main memory controller (14, 16) for each main memory (15, 17) of the system maintains a duplicate cache tag array (44, 46) containing current information on the status of data lines from that main memory that are stored in the cache memories (50, 52, 54). Thus, coherency checks can be performed directly by the main memory controller (14, 16). This eliminates the need for each processor having a cache memory to perform a separate coherency check and to communicate the results of its coherency checks to the main memory controller, and thereby reduces delays associated with processing coherent transactions.

    摘要翻译： 一种用于共享存储器多处理器计算机系统的改进的存储器系统，其中一个或多个处理器模块和/或输入/输出模块具有高速缓冲存储器（50,52,54）。 用于系统的每个主存储器（15,17）的主存储器控制器（14,16）保持包含关于存储在存储器中的主存储器的数据线的状态的当前信息的重复缓存标签阵列（44,46） 缓存存储器（50,52,54）。 因此，一致性检查可以由主存储器控制器（14,16）直接执行。 这消除了对具有高速缓冲存储器的每个处理器执行单独的一致性检查并将其一致性检查的结果传送到主存储器控制器的需要，从而减少与处理相干事务相关联的延迟。

    Multiprocessor data processing with cross interrogate synchronization mechanism
    83.
    发明公开
    Multiprocessor data processing with cross interrogate synchronization mechanism 失效
    采用交叉询问同步机制的多处理器数据处理

    公开(公告)号：EP0531004A3

    公开(公告)日：1994-03-02

    申请号：EP92307485.0

    申请日：1992-08-14

    申请人： International Business Machines Corporation

    发明人： Herzl, Robert Dov ,  Quinn, Linda Legault ,  Schroter, Russell Evan

    IPC分类号： G06F13/14 ,  G06F12/08

    CPC分类号： G06F12/0828 ,  G06F12/0822 ,  G06F13/14

    摘要： A mechanism prioritizes cross interrogate requests between multiple requestors in a multi-processor system where the delay due to cable length interconnecting requestors results in requests not being received within one machine cycle. Local and remote cross interrogate (XI) requests are latched up in storage control element (SCE) temporary registers before being prioritized. The local request is staged in a local delay register. The local request is selected from the local delay register by synchronization control logic, instead of the temporary register, when the remote request is issued one cycle earlier than the local request, or when both local and remote requests are issued at the same time, but the remote requests is from a master SCE. The staging of the local requests can be extended to multiple cycles, corresponding to the length of the cables between SCEs.

    摘要翻译： 一种机制优先于多处理器系统中的多个请求者之间的交叉询问请求，其中由于电缆长度互连请求者的延迟导致在一个机器周期内未接收到请求。 本地和远程交叉询问（XI）请求在优先化之前锁存在存储控制元素（SCE）临时寄存器中。 本地请求在本地延迟寄存器中进行。 当远程请求比本地请求提前一个周期发出时，或者同时发出本地请求和远程请求时，本地请求通过同步控制逻辑而不是临时寄存器从本地延迟寄存器中选择，但是 远程请求来自主SCE。 本地请求的分段可以延长到多个周期，对应于SCE之间的电缆长度。

    Hierarchical memory control system
    84.
    发明公开
    Hierarchical memory control system 失效
    Steuerungsanordnung eines等级Speichers。

    公开(公告)号：EP0468804A2

    公开(公告)日：1992-01-29

    申请号：EP91306831.8

    申请日：1991-07-26

    申请人： FUJITSU LIMITED

    发明人： Tone, Hirosada

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0822 ,  G06F12/0811

    摘要： A hierarchical memory control system comprising N central processing units (1) each including a store-in type buffer storage unit (2); a main storage unit (3) commonly used by the N central processing units (1); a global buffer storage unit (5) of a store-in type connected between the central processing units (1) and the main storage unit (3), for storing a data block transferred from the main storage unit (3), each entry of the global buffer storage unit (5) being larger than each entry of the buffer storage unit (2), the data block in each entry of the global buffer storage unit (5) being divided into M divided blocks; a tag unit (7) for managing the entries of the global buffer storage unit (5), including tags respectively corresponding to the entries of the global buffer storage unit (5), each tag including managing data for managing the data block; and a buffer control unit (8) for controlling the managing data in the tag unit (7), the buffer control unit (8) controlling the tag unit (7) and the global buffer storage unit (5) in such a way that, when the data stored in the buffer storage unit (2) is modified, the modified data is reflected at the global buffer storage unit (5) in accordance with the managing data in the tag unit (7), and when the data stored in the global buffer storage unit (5) is modified, the modified data is reflected at the main storage unit (3) in accordance with the managing data in the tag unit (7).

    摘要翻译： 一种分层存储器控制系统，包括N个中央处理单元（1），每个中央处理单元包括存储型缓冲存储单元（2）; 由N个中央处理单元（1）共同使用的主存储单元（3）; 连接在中央处理单元（1）和主存储单元（3）之间的存储型全局缓冲存储单元（5），用于存储从主存储单元（3）传送的数据块，每个条目 全局缓冲存储单元（5）大于缓冲存储单元（2）的每个条目，全局缓冲存储单元（5）的每个条目中的数据块被划分成M个分割块; 标签单元（7），用于管理全局缓冲存储单元（5）的条目，包括分别对应于全局缓冲存储单元（5）的条目的标签，每个标签包括用于管理数据块的管理数据; 以及用于控制标签单元（7）中的管理数据的缓冲器控制单元（8），缓冲器控制单元（8）以这样的方式控制标签单元（7）和全局缓冲存储单元（5） 当存储在缓冲存储单元（2）中的数据被修改时，修改的数据根据​​标签单元（7）中的管理数据在全局缓冲存储单元（5）反映，并且当存储在缓冲存储单元 全局缓冲存储单元（5）被修改，修改的数据根据​​标签单元（7）中的管理数据在主存储单元（3）处反映。

    Improved multiprocessor cache and method for maintaining coherence
    86.
    发明公开
    Improved multiprocessor cache and method for maintaining coherence 失效
    改进的多处理器缓存

    公开(公告)号：EP0355320A3

    公开(公告)日：1991-07-10

    申请号：EP89111606.3

    申请日：1989-06-26

    申请人： International Business Machines Corporation

    发明人： Liu, Lishing

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0822

    摘要： A method and apparatus for increasing cache concurrency in a multiprocessor system. In a multiprocessor system having a plurality of processors each having a local cache in order to increase concurrency the directory entry for a line in local cache will be assigned an LCH bit for locally changed status. If the last cache to hold the line had made a change to it this bit will be set on. If not, the bit will be off and thereby allow the receiving or requesting cache to make change to the line without requiring a main storage castout.

    Multi-processor caches with large granularity exclusivity locking
    87.
    发明公开
    Multi-processor caches with large granularity exclusivity locking 失效
    具有大颗粒度排他锁定的多处理器缓存

    公开(公告)号：EP0384102A2

    公开(公告)日：1990-08-29

    申请号：EP90100146.1

    申请日：1990-01-04

    申请人： International Business Machines Corporation

    发明人： Liu, Lishing

    IPC分类号： G06F12/08 ,  G06F9/46

    CPC分类号： G06F9/52 ,  G06F12/0822

    摘要： A tightly coupled multi-processor (MP) system is provided with large granularity locking of exclusivity in multi-processor caches. The unique access right for a processor P i is enforced by giving other central processors (CPs) a temporarily invalid (TI) state on block (B), even though some lines in the block (B) may still be resident in the cache. Any CP trying to access a block in the temporarily invalid (TI) state will need to talk to the storage control element (SCE) to obtain proper authorization (e.g., RO or EX state) on the block (B). Assuming that a central processor(CP) may have three states on a block (B), temporarily invalid TI B , read only RO B and exclusive EX B , TI B is the initial state for all blocks (B) at all central processors (CPs).

    摘要翻译： 紧密耦合的多处理器（MP）系统在多处理器高速缓存中具有大粒度锁定排他性。 即使块（B）中的某些行可能仍驻留在高速缓存中，对于处理器Pi的唯一访问权通过给予块（B）上的其他中央处理器（CP）暂时无效（TI）状态而得到实施。 试图访问处于暂时无效（TI）状态的块的任何CP都需要与存储控制元件（SCE）通信以获得块（B）上的适当授权（例如RO或EX状态）。 假定中央处理器（CP）在块（B）上可能具有三种状态，临时无效的TIB，只读ROB和独占EXB，则TIB是所有中央处理器（CP）处的所有块（B）的初始状态。

    Multiprocessor with independent direct cache-to-cache data transfers
    89.
    发明公开
    Multiprocessor with independent direct cache-to-cache data transfers 失效
    Mehrfachprozessor mitunabhängigerdirekter“Cache”zu“Cache”-Datenübertragung。

    公开(公告)号：EP0095598A2

    公开(公告)日：1983-12-07

    申请号：EP83104482.1

    申请日：1983-05-06

    申请人： International Business Machines Corporation

    发明人： Krygowski, Matthew Anthony ,  Messina, Benedicto Umberto ,  Silkman, William Dean

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0822

    摘要： In a data processing system having multiple processors with individual cache stores, a cross-interrogation is made in other caches if requested data is not found in the local associated cache. Data paths (67, 74, 83, 86, 201, 202, 203, 207, 208) and communication controls (20, 21, 22, 23, 50, 76, 77) are provided to enable direct cache-to-cache and cache-to-channel data transfers thus saving main storage accesses and the necessity to wait for main storage availability.

    摘要翻译： 在具有具有各个高速缓存存储器的多个处理器的数据处理系统中，如果在本地关联高速缓存中没有找到请求的数据，则在其他高速缓存中进行交叉询问。 提供数据路径（67,74,83,86,201,202,203,207,208）和通信控制（20,21,22,23,50,76,77）以实现直接缓存到缓存和高速缓存 - 频道数据传输，从而节省主存储访问以及等待主存储可用性的必要性。

    BROADCAST PROTOCOL FOR A NETWORK OF CACHES
    90.
    发明授权
    BROADCAST PROTOCOL FOR A NETWORK OF CACHES 有权
    用于高速缓存网络的广播协议

    公开(公告)号：EP2676203B1

    公开(公告)日：2018-01-10

    申请号：EP12747429.4

    申请日：2012-02-07

    申请人： ORACLE INTERNATIONAL CORPORATION

    发明人： LOEWENSTEIN, Paul N.

    IPC分类号： G06F12/0817 ,  G06F12/0831

    CPC分类号： G06F12/0831 ,  G06F12/0817 ,  G06F12/0822 ,  G06F12/0828

    摘要： A method for managing caches, including: broadcasting, by a first cache agent operatively connected to a first cache and using a first physical network, a first peer-to-peer (P2P) request for a memory address; issuing, by a second cache agent operatively connected to a second cache and using a second physical network, a first response to the first P2P request based on a type of the first P2P request and a state of a cacheline in the second cache corresponding to the memory address; issuing, by a third cache agent operatively connected to a third cache, a second response to the first P2P request; and upgrading, by the first cache agent and based on the first response and the second response, a state of a cacheline in the first cache corresponding to the memory address.