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    SYSTÈME DE ROUTAGE ACARS PAR PROFIL DE ROUTAGE
    83.
    发明公开
    SYSTÈME DE ROUTAGE ACARS PAR PROFIL DE ROUTAGE 有权
    有关路由PROFILES BASED ACARS路由系统

    公开(公告)号：EP2201703A2

    公开(公告)日：2010-06-30

    申请号：EP08805186.7

    申请日：2008-10-09

    申请人： AIRBUS OPERATIONS

    发明人： TAMALET, Stéphane ,  GOBBO, Gilles ,  DURAND, Frédéric ,  DEVILLE, Jean-Georges

    IPC分类号： H04B7/185 ,  H04L12/50 ,  H04L12/58

    CPC分类号： H04B7/18506 ,  H04L47/10 ,  H04W40/02

    摘要： The invention relates to a system for routing ACARS messages to a plurality of transmission media, intended to be installed on board an aircraft. The system includes: a database containing a plurality of routing profiles, each profile comprising a list indicating a preference ranking for each transmission medium; selection means for extracting a routing profile identifier from an ACARS message sending request and for selecting a transmission medium according to the preference ranking thereof from the routing profile stored in the database corresponding to said identifier. The transmission medium thus selected is then used to transmit the message.

    PATH REDUNDANT HARDWARE EFFICIENT COMMUNICATIONS INTERCONNECT SYSTEM
    84.
    发明公开
    PATH REDUNDANT HARDWARE EFFICIENT COMMUNICATIONS INTERCONNECT SYSTEM 有权
    与平衡冗余和程序，以皮带场通信AGENCY

    公开(公告)号：EP2186268A1

    公开(公告)日：2010-05-19

    申请号：EP08827466.7

    申请日：2008-08-08

    申请人： Smith, Robert B.

    发明人： Smith, Robert B.

    IPC分类号： H04L12/50

    CPC分类号： H04L49/1515 ,  H04L49/101 ,  H04L49/552

    摘要： A path redundant, hardware efficient communications interconnect (1) has embodiments that can present true any-to-any interconnect capability for first and second pathways (2) and (3) and can utilize double throw switches (25) with or without single throw switches (24) perhaps in staged collectives of sub arrays (4), (5), (6), (9), and (10). A loop-back communications interconnect (22) can be accomplished by an interleaved sub array (26). A quadrilateral center stage sub array (21) can be combined with asymmetric side stage sub arrays for hardware savings that are tenths of a percent of a traditional interconnect and even present eight fold savings over prior reduced hardware interconnects.

    SYSTEM AND METHOD FOR SWITCHING TRAFFIC THROUGH A NETWORK
    86.
    发明公开
    SYSTEM AND METHOD FOR SWITCHING TRAFFIC THROUGH A NETWORK 有权
    系统和方法的流量通过网络传输

    公开(公告)号：EP2087657A2

    公开(公告)日：2009-08-12

    申请号：EP07864928.2

    申请日：2007-11-29

    申请人： Level 3 Communications, LLC

    发明人： LAWRENCE, Joseph ,  GIBBINGS, Christopher ,  COMSTEDT, Niclas ,  EL-AAWAR, Nassar

    IPC分类号： H04L12/50

    CPC分类号： H04L49/15 ,  H04L49/1515 ,  H04L49/1523 ,  H04L49/35 ,  H04L49/602

    摘要： Embodiments of the present invention generally relate to network communications. More specifically, embodiments relate to a system and method for switching data through a network. An embodiment of a switching system communicatively couples an external network to a wide area network. The system includes a plurality of edge switches communicatively coupled to the external network, a plurality of core switches communicatively coupled to the wide area network, and an interconnected matπx of switches communicatively coupled to the core switches and the edge switches and configured to forward communication traffic between the edge switches and the core switches.

    SERVICE SWITCHING METHOD IN OPTICAL NETWORK,SYSTEM OF OPTICAL NETWORK,SWITCHING DEVICE AND NETWORK EDGING DEVICE OF THE PROVIDER
    87.
    发明公开
    SERVICE SWITCHING METHOD IN OPTICAL NETWORK,SYSTEM OF OPTICAL NETWORK,SWITCHING DEVICE AND NETWORK EDGING DEVICE OF THE PROVIDER 有权
    改变服务流程在供应商的光网络中，交换设备和网络边缘设备的光网络系统

    公开(公告)号：EP1998507A1

    公开(公告)日：2008-12-03

    申请号：EP07702199.6

    申请日：2007-01-25

    申请人： Huawei Technologies Co., Ltd.

    发明人： YI, Qiliang

    IPC分类号： H04L12/50

    CPC分类号： H04Q11/0062 ,  H04Q11/0067 ,  H04Q11/0071 ,  H04Q2011/0084 ,  H04Q2011/0088

    摘要： An optical network system disclosed in an embodiment of the present invention contains a PE and a handover equipment located between the PE and a CE. The PE is adapted to provide optical network access for the CE. The handover equipment is adapted to disconnect a CE that finishes working at a handover time, and/or connect a PE with a CE that will work in a next time segment. The present invention also discloses a service handover method of optical networks, in which a handover equipment is preset between a PE and a CE, and CE information in mutually complementing services and corresponding working time segments are pre-stored. The method includes: (A) determining a handover time according to the stored working time segments; and (B) upon arrival of the handover time, the handover equipment disconnects a CE that finishes working according to the stored CE information and the corresponding working time segments; and/or connects a CE that needs to communicate in a next working time segment with a corresponding PE. Furthermore, the present invention discloses a handover equipment and a PE in an optical network. The present invention can reduce the ports occupied by the PE.

    摘要翻译： 在对本发明实施例的游离缺失的光网络系统光盘包含PE和手放在位于PE和CE间的设备。 所述PE是angepasst以提供CE光网络接入。 移交设备angepasst断开一个CE没有完成在移交时间的工作，和/或在下一时间段thatwill工作CE连接PE。 因此，本发明光盘松光网络，其中切换设备在相互补充服务和相应的PE和CE，和CE之间信息预设的服务切换方法的工作时间段是预先存储的。 该方法包括：（A）确定的采矿的切换时间gemäß所存储的工作时间段; 和（B）的切换时间到达时，所述切换设备断开一个CE做饰面工作gemäß所存储的信息和所述CE对应的工作时间段; 和/或连接CE确实需要在接下来的时间段与对应的PE进行沟通。 进一步地，本发明盘松移交的设备和光网络的PE。 本发明可减少由PE占用的端口。

    ACCELERATED DATA SWITCHING ON SYMMETRIC MULTIPROCESSOR SYSTEMS USING PORT AFFINITY
    89.
    发明公开
    ACCELERATED DATA SWITCHING ON SYMMETRIC MULTIPROCESSOR SYSTEMS USING PORT AFFINITY 有权
    加速数据传输到使用连接AFFINITY对称多处理器系统

    公开(公告)号：EP1782583A2

    公开(公告)日：2007-05-09

    申请号：EP05778826.7

    申请日：2005-07-26

    申请人： Cisco Technology, Inc.

    发明人： KATHAIL, Pradeep ,  LOUGHEED, Kirk ,  BARACH, David ,  WINTERFIELD, Philip

    IPC分类号： H04L12/50

    CPC分类号： G06F9/5044

    摘要： A router that includes a plurality of processors (SMPs) where there is 'affinity' between particular processors and particular interfaces: Each of the router's interfaces are assigned to one of the processors. A packet arriving at a particular interface will be handled by the processor having an affinity to that particular interface. If the packet's egress is on an interface assigned to the same processor, then the output process will also be handled by that processor. If the egress interface has an affinity to a different processor, then the packet is handed over to the other processor for egress. The data structures that must be retrieved from memory to handle a packet are often associated with the interfaces through which the packet passes. Thus, having a particular processor handle all the packets that pass through a particular interface insures that the data structures needed to handle the packets will more likely be stored in the processor's cache and less likely be the object of inter-processor lock contention.