公开(公告)号：EP0581461A3

公开(公告)日：1996-05-01

申请号：EP93305345.6

申请日：1993-07-08

申请人： APTIX CORPORATION

发明人： Srinivasan, Adi ,  Cai, Hong ,  Guo, Ta-Pen

IPC分类号： H03K19/173 ,  H03K17/693 ,  H03K19/177

CPC分类号： H03K19/1776 ,  H03K17/693 ,  H03K19/17704 ,  H03K19/17736

摘要： A first user re-programmable interconnect architecture is provided wherein N switching elements are connected between selected interconnect conductors. The switching elements are controlled by M active storage elements, where M

公开(公告)号：EP0518701A3

公开(公告)日：1993-04-21

申请号：EP92305443.1

申请日：1992-06-12

申请人： APTIX CORPORATION

发明人： Osann, Robert, Jr. ,  Shaw, George A., Jr. ,  Mohsen, Amr M.

IPC分类号： G06F15/60 ,  H05K1/00

CPC分类号： H01L23/5382 ,  H01L2224/49171 ,  H01L2924/10253 ,  H05K1/0289 ,  H05K1/112 ,  H05K2201/09945 ,  H05K2201/10689 ,  H05K2203/175 ,  H01L2924/00

摘要： The invention uses a programmable interconnect substrate having a plurality of conductive and interconnectable vias located on one or both surfaces thereof. A customised pattern of bonding pads is then formed over the one or both surface of the substrate which correspond to the terminal footprints of specific surface mounted packages intended to be mounted on the substrate. A generalised pattern of bonding pads may also be formed on the surface of the substrate for electrically connecting terminals of bare dice thereto by means of thin wire. All bonding pads are electrically connected to one or more vias by direct electrical contact or by a conductive trace extending from the bonding pad to a nearly via.

摘要翻译： 本发明使用具有位于其一个或两个表面上的多个导电和可互连通孔的可编程互连基板。 然后在衬底的一个或两个表面上形成定制的焊盘图案，该表面对应于期望安装在衬底上的特定表面安装封装的端子脚印。 也可以在基板的表面上形成接合焊盘的一般化图案，用于通过细线电连接裸芯片的端子。 所有接合焊盘通过直接电接触或通过从接合焊盘延伸到几乎通孔的导电迹线而电连接到一个或多个通孔。

公开(公告)号：EP0575186A3

公开(公告)日：1994-06-22

申请号：EP93304756.5

申请日：1993-06-17

申请人： APTIX CORPORATION

发明人： Guo, Ta-Pen ,  Srinivasan, Adi

IPC分类号： H03K19/017 ,  G11C11/419 ,  G11C8/00

CPC分类号： H03K19/01721

摘要： A pullup circuit for use with plurality of N-Channel pulldown transistors (14a,..., 14n) connected to a bit line (12) includes a P-channel MOS pullup transistor (10) connected between the bit line (12) and a voltage rail (V DD ). An inverter (32) is connected between the bit line (12) and the drain of an N-Channel MOS transistor (34) having its gate connected to the voltage rail (V DD ) and its source connected to the gate of the P-Channel MOS pullup transistor (10). A first P-Channel MOS transistor (36) is connected between the voltage rail (V DD ) and the gate of the P-Channel MOS pullup transistor (10). A second P-Channel MOS transistor (38) having its gate connected to ground is connected between the bit line (12) and the gate of the first P-Channel MOS transistor (10). Four P-Channel MOS divider transistors (40,42,44,46) are connected between the drain of the first P-Channel MOS transistor (10) and ground. The gates of the P-Channel MOS divider transistors (40,42,44,46) are connected together to ground. The P-Channel MOS pullup transistor (10) and the N-Channel MOS pulldown transistors (14a,...,14n) are large. The first and second P-Channel MOS transistors (36,38), the first N-Channel MOS transistor (34), and the P-Channel MOS divider transistors (40,42,44,46) are close to minimum size. The P-Channel and N-Channel devices comprising the inverter devices are larger than minimum size.

公开(公告)号：EP0581461A2

公开(公告)日：1994-02-02

申请号：EP93305345.6

申请日：1993-07-08

申请人： APTIX CORPORATION

发明人： Srinivasan, Adi ,  Cai, Hong ,  Guo, Ta-Pen

IPC分类号： H03K19/173 ,  H03K17/693 ,  H03K19/177

CPC分类号： H03K19/1776 ,  H03K17/693 ,  H03K19/17704 ,  H03K19/17736

摘要： A first user re-programmable interconnect architecture is provided wherein N switching elements are connected between selected interconnect conductors. The switching elements are controlled by M active storage elements, where M

摘要翻译： 第一用户重新可编程互连架构worin连接所选互连导体之间的N个开关元件提供。 所述开关元件由M个有源存储元件，其中，M

公开(公告)号：EP0581443A2

公开(公告)日：1994-02-02

申请号：EP93305068.4

申请日：1993-06-29

申请人： APTIX CORPORATION

发明人： Guo, Ta-Pen ,  Srinivasan, Adi

IPC分类号： G11C7/00

CPC分类号： G11C7/20

摘要： Apparatus for forcing a memory cell to a known state upon power-up includes circuitry for providing two signals PWRUP and PWRUPB which are used during chip power-up. At power-up, as V cc rises from 0 volt to 3.5 volts, the PWRUP signal follows V cc and the PWRUPB signal maintains 0 volts. The PWRUP and PWRUPB signals are used to drive the gates of P-Channel and N-Channel MOS transistors, respectively, including pass gates connected between word line driver circuits and bit line driver circuits driving the word lines and bit lines associated with the memory cells. In addition, the PWRUPB signal is used to drive P-Channel MOS pullup transistors connected between the word lines and V cc and the bit lines and V cc . During power-up, the pass gates are disabled, disconnecting the word lines and bit lines from their drivers. The word lines and bit lines are forced to follow the rise of V cc by the P-Channel pullup transistors. When V cc reaches its desired value, the PWRUP signal goes to 0 volts and the PWRUPB signal goes to V cc , thus turning on the pass gates to connect the word line and bit line driver circuits to the word lines and bit lines. The V cc final PWRUPB signal turns off the P-Channel MOS pullup transistors connected between the word lines and V cc and the bit lines and Vcc.

公开(公告)号：EP0481703B1

公开(公告)日：2003-09-17

申请号：EP91309424.9

申请日：1991-10-14

申请人： APTIX CORPORATION

发明人： Mohsen, Amr M.

IPC分类号： H01L23/538

CPC分类号： H01L22/22 ,  G01R31/2853 ,  G01R31/2884 ,  G01R31/318505 ,  G01R31/318538 ,  G11C29/30 ,  H01L23/5252 ,  H01L23/528 ,  H01L23/5382 ,  H01L2924/0002 ,  H05K1/0286 ,  H01L2924/00

公开(公告)号：EP0437980A2

公开(公告)日：1991-07-24

申请号：EP90314409.5

申请日：1990-12-28

申请人： APTIX CORPORATION

发明人： Mohsen, Amr M.

IPC分类号： H05K1/00 ,  H05K3/00

CPC分类号： H01L23/5382 ,  H01L2924/0002 ,  H05K1/029 ,  H05K1/0298 ,  H05K2203/175 ,  H01L2924/00

摘要： A printed circuit board contacts a plurality of component contacts for receipt of electronic components and a plurality of electrically conductive traces, each trace being electrically connected to a corresponding one of the component contacts. A corresponding plurality of interconnect holes is formed on a selected portion of the printed circuit board with each interconnect hole contacting uniquely a corresponding one of the plurality of electrically conductive traces. A multiplicity of custom conductive traces (106) is then formed in an interconnect region such that each of the multiplicity of conductive traces interconnects at least one of the interconnect holes to at least one other interconnect hole thereby to form an electrically conductive path between each of the interconnect holes interconnected by the custom conductive traces. A user is thus able to achieve a desired electrical function from the electronic components to be connected to the printed circuit board.

摘要翻译： 印刷电路板接触多个组件触点以接收电子部件和多个导电迹线，每个迹线电连接到相应的一个部件触点。 在印刷电路板的选定部分上形成相应的多个互连孔，每个互连孔唯一地接触多个导电迹线中相应的导电迹线。 然后在互连区域中形成多个定制导电迹线（106），使得多个导电迹线中的每一个将至少一个互连孔互连至至少一个其它互连孔，从而在每个之间形成导电路径 互连孔由定制导电迹线互连。 因此，用户能够从要连接到印刷电路板的电子部件获得期望的电功能。

公开(公告)号：EP0419232A2

公开(公告)日：1991-03-27

申请号：EP90310252.3

申请日：1990-09-19

申请人： APTIX CORPORATION

发明人： Mohsen, Amr M.

IPC分类号： G06F15/60 ,  H05K3/00 ,  H05K1/00 ,  H01L23/525

CPC分类号： G06F17/5027 ,  G01R31/2818 ,  G06F17/5068 ,  H01L23/525 ,  H01L2924/0002 ,  H05K1/029 ,  H05K1/0298 ,  H05K3/222 ,  H05K3/429 ,  H05K2201/10212 ,  H05K2201/10689 ,  H01L2924/00

摘要： A field programmable printed circuit board is provided which includes a multiplicity of component contacts for making electrical contact to the leads of electronic components to be mounted on the printed circuit board, a corresponding multiplicity of interconnect contacts for receipt of the leads on the package or packages of a programmable integrated circuit or circuits for interconnecting as desired the electronic components, and one or more layers of conductive traces formed on the printed circuit board, each conductive trace uniquely connecting electrically one component contact to one interconnect contact.

摘要翻译： 提供了现场可编程印刷电路板，其包括用于与要安装在印刷电路板上的电子部件的引线电接触的多个部件触点，用于接收封装或封装上的引线的相应多个互连触点 用于根据需要互连电子部件的可编程集成电路或用于形成在印刷电路板上的一层或多层导电迹线的电路，每个导电迹线将电气单一元件触点唯一地连接到​​一个互连触点。

公开(公告)号：EP0581443A3

公开(公告)日：1995-04-19

申请号：EP93305068.4

申请日：1993-06-29

申请人： APTIX CORPORATION

发明人： Guo, Ta-Pen ,  Srinivasan, Adi

IPC分类号： G11C7/00

CPC分类号： G11C7/20

摘要： Apparatus for forcing a memory cell to a known state upon power-up includes circuitry for providing two signals PWRUP and PWRUPB which are used during chip power-up. At power-up, as V cc rises from 0 volt to 3.5 volts, the PWRUP signal follows V cc and the PWRUPB signal maintains 0 volts. The PWRUP and PWRUPB signals are used to drive the gates of P-Channel and N-Channel MOS transistors, respectively, including pass gates connected between word line driver circuits and bit line driver circuits driving the word lines and bit lines associated with the memory cells. In addition, the PWRUPB signal is used to drive P-Channel MOS pullup transistors connected between the word lines and V cc and the bit lines and V cc . During power-up, the pass gates are disabled, disconnecting the word lines and bit lines from their drivers. The word lines and bit lines are forced to follow the rise of V cc by the P-Channel pullup transistors. When V cc reaches its desired value, the PWRUP signal goes to 0 volts and the PWRUPB signal goes to V cc , thus turning on the pass gates to connect the word line and bit line driver circuits to the word lines and bit lines. The V cc final PWRUPB signal turns off the P-Channel MOS pullup transistors connected between the word lines and V cc and the bit lines and Vcc.

摘要翻译： 用于在上电时将存储器单元强制为已知状态的装置包括用于提供在芯片上电期间使用的两个信号PWRUP和PWRUPB的电路。 上电时，当VCC从0伏升至3.5伏时，PWRUP信号跟随VCC，PWRUPB信号保持0伏。 PWRUP和PWRUPB信号分别用于驱动P沟道和N沟道MOS晶体管的栅极，包括连接在字线驱动电路和驱动与存储单元相关联的字线和位线的位线驱动电路之间的通路 。 此外，PWRUPB信号用于驱动连接在字线和VCC与位线和VCC之间的P沟道MOS上拉晶体管。 在上电期间，禁止通过门，将字线和位线与驱动器断开。 字线和位线被迫通过P沟道上拉晶体管跟随VCC的上升。 当VCC达到所需值时，PWRUP信号变为0伏，PWRUPB信号变为VCC，从而打开通过门，将字线和位线驱动电路连接到字线和位线。 VCC最终PWRUPB信号关闭连接在字线和VCC与位线和VCC之间的P沟道MOS上拉晶体管。

公开(公告)号：EP0575188A1

公开(公告)日：1993-12-22

申请号：EP93304759.9

申请日：1993-06-17

申请人： APTIX CORPORATION

发明人： Guo, Ta-Pen ,  Srinivasan, Adi

IPC分类号： G11C11/412

CPC分类号： H03K3/356156 ,  G11C11/412

摘要： A level-shifting static random memory cell includes a first stage having a first P-Channel MOS transistor having its source connected to a high voltage supply rail, and its drain connected to the drain of a first N-Channel MOS transistor. The source of the first N-Channel MOS transistor is connected to the drain of a second N-Channel MOS transistor. The source of the second N-channel MOS transistor is connected to a VSS power supply rail. A second stage comprises a second P-Channel MOS transistor having its source connected to the high voltage supply rail V HS , and its drain connected to the drain of a third N-Channel MOS transistor. The source of the third N-Channel MOS transistor is connected to the drain of a fourth N-Channel MOS transistor. The source of the fourth N-channel MOS transistor is connected to VSS. The gates of the first and second P-Channel MOS transistors are cross coupled and the gates of the second and fourth N-Channel MOS transistors are cross coupled. The gates of the first and third N-channel MOS transistors are connected together to power supply rail V DD , usually 5 volts. The first and second P-channel MOS transistors are formed in an n-well biased at power supply voltage V HS . A bit line coupled to the drain of the second N-Channel MOS transistor through a fifth N-Channel MOS transistor, having its gate connected to a word line.

摘要翻译： 电平移动静态随机存储单元包括具有其源极连接到高压电源轨的第一P沟道MOS晶体管的第一级，其漏极连接到第一N沟道MOS晶体管的漏极。 第一N沟道MOS晶体管的源极连接到第二N沟道MOS晶体管的漏极。 第二N沟道MOS晶体管的源极连接到VSS电源轨。 第二级包括其源极连接到高电压电源轨VHS的第二P沟道MOS晶体管，其漏极连接到第三N沟道MOS晶体管的漏极。 第三N沟道MOS晶体管的源极连接到第四N沟道MOS晶体管的漏极。 第四个N沟道MOS晶体管的源极连接到VSS。 第一和第二P沟道MOS晶体管的栅极交叉耦合，并且第二和第四N沟道MOS晶体管的栅极交叉耦合。 第一和第三N沟道MOS晶体管的栅极连接到电源轨VDD，通常为5伏。 第一和第二P沟道MOS晶体管形成在电源电压VHS中以n-阱偏置。 通过第五N沟道MOS晶体管耦合到第二N沟道MOS晶体管的漏极的位线，其栅极连接到字线。