公开(公告)号：EP2997627A2

公开(公告)日：2016-03-23

申请号：EP14797227.7

申请日：2014-05-14

Applicant: MC10, INC.

Inventor： HSU, Yung-Yu ,  WORK, John ,  DOWLING, Kevin J.

IPC: H01R9/00

CPC classification number: H05K1/0283 ,  A61B5/0059 ,  A61B5/6846 ,  A61B2562/164 ,  H01L23/145 ,  H01L23/5386 ,  H01L23/5387 ,  H01L2924/15791 ,  H05K1/189 ,  H05K2201/0133 ,  H05K2201/0394 ,  H05K2201/09263 ,  H05K2201/09945

Abstract: An example stretchable device is described that includes electrical contacts and an interconnect coupling the electrical contacts. The interconnect has a meander-shaped configuration that includes at least one nested serpentine-shaped feature. The interconnect can be conductive or non-conductive. The meander-shaped configuration can be a serpentine structure, providing a serpentine-in-serpentine configuration.

Abstract translation: 描述了一个示例性可拉伸装置，其包括电触点和耦合电触点的互连。 互连具有曲折形状，其包括至少一个嵌套的蛇形特征。 互连可以是导电的或不导电的。 曲折形状可以是蛇形结构，提供蛇形蛇形结构。

公开(公告)号：EP1653787A1

公开(公告)日：2006-05-03

申请号：EP05292274.7

申请日：2005-10-27

Applicant: Koyo Seiko Co., Ltd.

Inventor： Temba, Koji, Koyo Seiko co., Ltd.

IPC: H05K1/00

CPC classification number: H01L21/485 ,  H01L23/5382 ,  H01L2924/0002 ,  H05K1/0287 ,  H05K1/0289 ,  H05K3/328 ,  H05K2201/09681 ,  H05K2201/09945 ,  H05K2203/175 ,  Y10T29/49126 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A wiring board is manufactured by a step of forming a meshy cylindrical body 2, where plural conductive rings 1 are connected to each other at plural positions in the respective peripheral direction, a step of forming laminated meshy sheets 3 and 4, by squashing the meshy cylindrical body 2 in the radial direction, a step of inserting an insulation sheet 5 between the meshy sheets 3 and 4, and a step of forming lacking portions 6 at a position in the peripheral direction of conductive rings 1a, 1b of the meshy sheets 3 and 4. It becomes possible to directly join a semiconductor chip 7 to the conductive ring 1a of the meshy sheet 3, and therefore, a wiring circuit can be obtained without using a solder joint.

Abstract translation: 通过形成网状圆筒体2的步骤制造布线板，其中多个导电环1在各个周向的多个位置彼此连接，通过挤压网状层叠网状片3和4的步骤 圆筒体2在径向方向上，将绝缘片5插入在网状片材3和4之间的步骤，以及在网状片材3的导电环1a，1b的周向方向上形成缺少部分6的步骤 可以将半导体芯片7直接接合到网状片材3的导电性环1a上，因此可以不使用焊点而获得布线电路。

公开(公告)号：EP0721659B1

公开(公告)日：2000-11-02

申请号：EP94926565.6

申请日：1994-08-24

Applicant: MINNESOTA MINING AND MANUFACTURING COMPANY

Inventor： KOSKENMAKI, David, C. ,  CALHOUN, Clyde, D.

IPC: H01L21/48

CPC classification number: H01L24/83 ,  B23K35/0222 ,  H01L23/49883 ,  H01L24/29 ,  H01L2224/29298 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/0781 ,  H01L2924/09701 ,  H01L2924/12033 ,  H01L2924/14 ,  H05K3/102 ,  H05K3/323 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2201/10719 ,  H05K2203/0338 ,  H05K2203/0425 ,  H05K2203/128 ,  Y10T428/12 ,  Y10T428/12014 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929

Abstract: The present invention provides a method for providing an array of metal microbeads on a substrate, preferably in a regular pattern of very fine, uniform size microspheres or microbeads at precise spacing or scale previously unachievable. The method of the present invention comprises the steps of providing a metal layer (14) on a substrate (12) that is partitioned into metal regions (20); heating the metal layer to a temperature sufficient to melt the metal and to permit beading of the layer into discrete microbeads (22).

公开(公告)号：EP1021938A1

公开(公告)日：2000-07-26

申请号：EP98938474.8

申请日：1998-08-10

Applicant: FRY'S METALS, INC.

Inventor： ARTHUR, Richard ,  HOLT, Lyn ,  BAGHURST, David ,  NICHOLLS, Gary, Lee

IPC: H05K3/40 ,  H05K3/32

CPC classification number: H05K3/4069 ,  H01R43/007 ,  H05K3/321 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/09572 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2203/0126 ,  H05K2203/0191 ,  H05K2203/0278 ,  H05K2203/1572 ,  Y10T156/1057

Abstract: A process for the preparation of an anisotropic conducting material, which process comprises the steps of: (i) providing a strip or sheet (10) of a non-conducting matrix and laminating to each side thereof at least one layer of a release material (11, 12) in order to form a composite matrix (13); (ii) forming an array of holes (14) in a predetermined pattern in the composite matrix (13) from step (i); (iii) passing the matrix (13) from step (ii) through a coating head (1) which simultaneously fills the holes (14) of the array in the composite matrix (13) from both sides of the said matrix (13) with a conducting material (15); (iv) curing or drying the composite filled matrix from step (iii); and (v) removing at least one layer of release material (11, 12) from each side of the matrix.

公开(公告)号：EP0726621B1

公开(公告)日：2000-05-10

申请号：EP96300697.8

申请日：1996-01-31

Applicant: AT&T Corp.

Inventor： Fastnacht, Richard A. ,  Zhu, Wei ,  Jin, Sungho

IPC: H01R12/22 ,  H01L21/48 ,  H05K3/34 ,  H01R43/00 ,  H01L23/498

CPC classification number: H01R13/2407 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H01R12/714 ,  H01R43/007 ,  H05K3/105 ,  H05K3/3436 ,  H05K3/4038 ,  H05K3/4069 ,  H05K2201/09945 ,  H05K2201/10378 ,  Y02P70/613 ,  Y10S505/739 ,  H01L2924/00

公开(公告)号：EP0834921A2

公开(公告)日：1998-04-08

申请号：EP97203302.1

申请日：1992-12-30

Applicant: TESSERA, INC.

Inventor： Distefano, Thomas H. ,  Khandros, Igor ,  Grube, Gary W. ,  Ehrenberg, Scott G.

IPC: H01L23/538

CPC classification number: H05K3/462 ,  H01L21/4857 ,  H01L23/5383 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01R12/523 ,  H05K1/0287 ,  H05K1/029 ,  H05K1/0298 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4623 ,  H05K2201/0195 ,  H05K2201/0305 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2201/10666 ,  H05K2203/175 ,  H01L2924/00

Abstract: The invention relates to a method of making a multi-layer circuit assembly. Said method comprises the steps of providing a first circuit panel (544) having a dielectric body with oppositely directed top and bottom surfaces, contacts (538) on its top surface at locations of a first pattern, terminals (530) on its bottom surface, and through-conductors (527) electrically connected to said terminals and extending to the top surface of the panel, and a second circuit panel (562) having a dielectric body with a bottom surface and terminals (530) at locations of said first pattern on the bottom surface of such panel, said providing step including the step of customizing said first circuit panel by selectively treating the top surface of such panel so that less than all of the through conductors of such panel are connected to contacts of such panel; stacking said circuit panels in superposed, top-surface to bottom surface relation so that the top surface of said first circuit panel faces the bottom surface of said second circuit panel at a first interface and said first patterns on said facing surfaces are in registration with one another, with said contacts of said first panel being aligned with said terminals of said second panel at least some locations of said inregistration patterns; and non-selectively connecting all of said aligned contacts and terminals at said interface, whereby less than all of said through conductors of said customized panel are connected to terminals of said adjacent panel. The invention also relates to a multi-layer circuit assembly.

Abstract translation: 本发明涉及一种制造多层电路组件的方法。 所述方法包括以下步骤：提供具有电介质体的第一电路面板（544），所述电介质体具有相反指向的顶部和底部表面，其顶表面上的第一图案位置处的触点（538），其底表面上的端子（530） 和电连接到所述端子并延伸到所述面板的顶表面的贯穿导体（527），以及第二电路板（562），所述第二电路板（562）具有电介质体，所述电介质体具有底表面和在所述第一图案的位置处的端子 所述提供步骤包括定制所述第一电路板的步骤，所述步骤通过选择性地处理所述板的顶部表面以使得所述板的所有贯通导体都少于所述板的触点连接; 将所述电路面板叠置成叠置的顶面到底面关系，使得所述第一电路面板的顶面在第一界面处面向所述第二电路面板的底面，并且在所述面对的表面上的所述第一图案与一个 另一方面，所述第一面板的所述触点与所述第二面板的所述端子对准所述对齐图案的至少一些位置; 并且在所述接口处非选择性地连接所有所述对齐的触点和端子，由此所述定制面板的少于所有的所述贯通导体连接到所述相邻面板的端子。 本发明还涉及一种多层电路组件。

公开(公告)号：EP0687137A2

公开(公告)日：1995-12-13

申请号：EP95303635.7

申请日：1995-05-30

Applicant: AT&T Corp.

Inventor： Jin, Sungho ,  McCormack, Mark Thomas

IPC: H05K3/34 ,  B23K35/02

CPC classification number: B23K35/0222 ,  B23K35/0227 ,  B23K35/0244 ,  H01L2924/0002 ,  H05K3/3436 ,  H05K2201/0215 ,  H05K2201/083 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2201/10424 ,  H05K2203/0235 ,  H05K2203/0769 ,  H05K2203/104 ,  Y02P70/613 ,  H01L2924/00

Abstract: Electronic devices having at least two components (53,55) with mating contact pads (52,54) are provided with high-aspect-ratio solder joints between the mating pads. These joints are formed by placing a composite solder medium (51) containing solder wires (56) in an electrically insulating matrix (57) such that at least two solder wires (56) are in contact with the mating pads (52,54), and fusing the wires (56) to the pads. The insulating matrix (57) with remainder of solder wires (56) is then optionally removed from between the said at least two components (53,55). The composite solder medium (51) is formed by preparing an elongated body of solder wires in an insulating matrix and cutting off slices of the composite solder medium, the solder wires having a high-aspect-ratio of length to their diameter. Alternatively sheets of the composite solder medium are prepared by magnetically aligning solder coated magnetic particles into columns arranged transverse of an insulating matrix and heating sufficiently to fuse the solder in each column into a continuously conducting solder path.

Abstract translation: 具有至少两个具有配合接触垫的部件的电子设备在配合焊盘之间设置有高纵横比焊接点。 这些接头通过将包含焊丝的复合焊料介质放置在电绝缘基体中而形成，使得至少两个焊丝与配合焊盘接触，并将焊丝熔合到焊盘。 然后可选地从所述至少两个部件之间移除具有剩余焊丝的绝缘基体。 复合焊料介质通过在绝缘基体中制备细长的焊丝体并且切断复合焊料介质的切片而形成，该焊丝具有与其直径的长宽比的高纵横比。 或者，复合焊料介质的片材通过将焊接涂覆的磁性颗粒磁性地对准到横向于绝缘矩阵的列并且充分加热以将每个列中的焊料熔合成连续导电的焊接路径来制备。

公开(公告)号：EP0518701A2

公开(公告)日：1992-12-16

申请号：EP92305443.1

申请日：1992-06-12

Applicant: APTIX CORPORATION

Inventor： Osann, Robert, Jr. ,  Shaw, George A., Jr. ,  Mohsen, Amr M.

IPC: G06F15/60 ,  H05K1/00

CPC classification number: H01L23/5382 ,  H01L2224/49171 ,  H01L2924/10253 ,  H05K1/0289 ,  H05K1/112 ,  H05K2201/09945 ,  H05K2201/10689 ,  H05K2203/175 ,  H01L2924/00

Abstract: The invention uses a programmable interconnect substrate having a plurality of conductive and interconnectable vias located on one or both surfaces thereof. A customised pattern of bonding pads is then formed over the one or both surface of the substrate which correspond to the terminal footprints of specific surface mounted packages intended to be mounted on the substrate. A generalised pattern of bonding pads may also be formed on the surface of the substrate for electrically connecting terminals of bare dice thereto by means of thin wire. All bonding pads are electrically connected to one or more vias by direct electrical contact or by a conductive trace extending from the bonding pad to a nearly via.

Abstract translation: 本发明使用具有位于其一个或两个表面上的多个导电和可互连通孔的可编程互连基板。 然后在衬底的一个或两个表面上形成定制的焊盘图案，该表面对应于期望安装在衬底上的特定表面安装封装的端子脚印。 也可以在基板的表面上形成接合焊盘的一般化图案，用于通过细线电连接裸芯片的端子。 所有接合焊盘通过直接电接触或通过从接合焊盘延伸到几乎通孔的导电迹线而电连接到一个或多个通孔。

公开(公告)号：EP0329414A3

公开(公告)日：1991-02-06

申请号：EP89301441.5

申请日：1989-02-15

Applicant: BICC Public Limited Company

Inventor： Lawrence, Howard

IPC: H05K1/00 ,  H05K3/10 ,  H05K3/36 ,  H05K3/40 ,  H05K1/11

CPC classification number: H05K3/326 ,  H05K1/0287 ,  H05K1/0298 ,  H05K1/118 ,  H05K3/0058 ,  H05K3/306 ,  H05K3/4046 ,  H05K3/4611 ,  H05K2201/091 ,  H05K2201/09454 ,  H05K2201/096 ,  H05K2201/09945 ,  H05K2201/10303 ,  H05K2201/1059 ,  H05K2201/2009

Abstract: A printed circuit board which is of such a construction that patterns of electrically conductive strips and/or pads of either standard or non-standard form can be readily provided comprises a rigid board 1 of which at least the major surfaces are of electrically insulating material, which has extending through the board a multiplicity of holes 2 arranged in a pattern of rows and columns and which carries on one or each of its major surfaces a multiplicity of annular metal islands 3 each bounding a hole in the board and discrete with respect to the other annular islands. The rigid board 1 may also carry on said one or each of its major surfaces supplementary metal islands 4 and 5 each positioned between and discrete with respect to annular islands bounding adjacent holes in the rigid board. A circuit of either a standard or non-standard pattern can be formed by electrically interconnecting selected adjacent metal islands 3, 4 and 5 with local deposits of material of high electrical conductivity in such a way as to bridge the gap between adjacent islands. The local deposits may be effected manually but are preferably effected automatically using a modified computer aided design plotter or an automatic fluid dispensing machine.

Abstract translation: 具有这样一种结构的印刷电路板，即可容易地提供标准或非标准形式的导电条和/或焊盘的图案，其中至少主表面为电绝缘材料的刚性板1， 其沿着板延伸了多个以行和列的图案布置的孔2，并且在其主表面中的一个或多个表面上具有多个环形金属岛3，每个环形金属岛3围绕板中的孔并且相对于 其他环岛。 刚性板1还可以承载其主要表面中的一个或每个主要附加金属岛4和5，其各自位于相对于限定刚性板中相邻孔的环形岛之间和离散。 标准或非标准图案的电路可以通过将所选择的相邻金属岛3,4和5与当前存在高导电性材料的局部沉积物以互相连接相邻岛之间的间隙的方式形成。 局部沉积可以手动进行，但优选使用改进的计算机辅助设计绘图仪或自动流体分配机器自动实现。

公开(公告)号：EP0074303B1

公开(公告)日：1986-02-26

申请号：EP82401565.5

申请日：1982-08-23

Applicant: Rouge, François

Inventor： Rouge, François

IPC: H05K1/00 ,  H05K3/46

CPC classification number: H05K1/0287 ,  H05K1/0298 ,  H05K3/429 ,  H05K2201/09609 ,  H05K2201/09945