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    INTEGRATED CLOCK GATING CELL FOR CIRCUITS WITH DOUBLE EDGE TRIGGERED FLIP-FLOPS
    2.
    发明公开
    INTEGRATED CLOCK GATING CELL FOR CIRCUITS WITH DOUBLE EDGE TRIGGERED FLIP-FLOPS 审中-公开
    随着集成电路定时时钟小区双边沿控制FLOPS

    公开(公告)号：EP2507911A1

    公开(公告)日：2012-10-10

    申请号：EP10835099.2

    申请日：2010-12-02

    申请人： Cadence Design Systems, Inc.

    发明人： ZLATANOVICI, Radu ,  SUBRAMANI, Kumar

    IPC分类号： H03K3/00

    CPC分类号： H03K3/356156 ,  H03K3/012

    摘要： A double edge triggered circuit includes a clock gater responsive to a clock signal and an enable signal to output a gated clock signal, a first double edge triggered flip-flop that launches a data signal in response to the gated clock signal, and a second double edge triggered flip-flop that captures the data signal in response to the clock signal, wherein the clock gater stops the gated clock signal at a first logic value when the enable signal is at a first logic state, and the clock gater switches the gated clock signal from the first logic value at a next clock edge when the enable signal is at a second logic state.

    A logic level shifter with integrated latch
    4.
    发明公开
    A logic level shifter with integrated latch 审中-公开
    用于具有集成锁存执行逻辑电平的电路装置

    公开(公告)号：EP1191694A1

    公开(公告)日：2002-03-27

    申请号：EP01000400.0

    申请日：2001-08-22

    申请人： Texas Instruments Incorporated

    发明人： Ovens, Kevin M. ,  Shinham, Thomas C.

    IPC分类号： H03K19/0185 ,  H03K3/356

    CPC分类号： H03K3/35625 ,  H03K3/356156 ,  H03K19/018521 ,  H03K19/01855

    摘要： An integrated circuit (IC) comprising an integrated level shifting latch 306 for I/O. The level shift in the IC I/O section may be clocked. In addition, a latch (comprised of transistors m11-m14) may be moved from the core section 300 to the I/O section 302 of the device, and thus the incoming clock 308 may remain in the external voltage domain to clock the latch along with the level shift. The level shift and latch may be clocked on opposite phases of the clock. Preferably, the level shift and latch may operate differentially on the data signal. Both setup and clock-to-Q times are significantly reduced with respect to prior art devices, allowing higher speed industry specifications may be met.

    MEMORY INCLUDING RESISTOR BIT-LINE LOADS
    6.
    发明授权
    MEMORY INCLUDING RESISTOR BIT-LINE LOADS 失效
    存储器，包括电阻器双线负载

    公开(公告)号：EP0929896B1

    公开(公告)日：2001-11-28

    申请号：EP97944574.9

    申请日：1997-09-29

    申请人： Advanced Micro Devices, Inc.

    发明人： HOLST, John, Christian

    IPC分类号： G11C7/00 ,  G11C17/12

    CPC分类号： G11C29/026 ,  G11C7/00 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/14 ,  G11C11/401 ,  G11C11/4087 ,  G11C11/41 ,  G11C11/412 ,  G11C11/418 ,  G11C16/04 ,  G11C17/14 ,  G11C29/02 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/18 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004 ,  G11C2029/5006 ,  H03K3/356156 ,  H03K5/13 ,  H03K2005/00019 ,  H03K2005/00071 ,  H03L7/08 ,  H03L7/0995

    摘要： A memory includes a data bit line and a reference bit line. Word lines in the memory are connected to the bit lines by transistors. The transistors on data bit lines and the reference bit lines are substantially the same size. The capacitances on the data bit lines are substantially the same as the capacitances on the reference bit lines. When the word line is activated, the bit lines express a steady-state voltage that is a function of the resistance of the bit lines. In one example, the data bit lines have a resistance (R) and the reference bit lines have half the resistance (R2). The same current is sourced to the data bit lines and the reference bit lines so that the steady-state voltage of the data bit line differs from the steady-state voltage of the reference bit line by a factor equal to the ratio of the resistances. The resistors (R and R2) perform two functions, the resistors clamp level of the bit lines that are being discharged to stop the displacement current. The data bit lines are sensed differentially with respect to the reference.

    摘要翻译： 存储器包括数据位线和参考位线。 存储器中的字线通过晶体管连接到位线。 数据位线和参考位线上的晶体管大小基本相同。 数据位线上的电容基本上与参考位线上的电容相同。 当字线被激活时，位线表示作为位线电阻的函数的稳态电压。 在一个示例中，数据位线具有电阻（R）并且参考位线具有电阻的一半（R2）。 相同的电流源于数据位线和参考位线，使得数据位线的稳态电压与参考位线的稳态电压相差等于电阻比的因子。 电阻（R和R2）执行两个功能，电阻钳位正在放电的位线的电平以停止位移电流。 数据位线相对于参考差分地被感测。

    Latch circuit capable of reducing slew current
    7.
    发明公开
    Latch circuit capable of reducing slew current 失效
    为了降低横流启用锁存电路

    公开(公告)号：EP0872956A3

    公开(公告)日：2000-02-23

    申请号：EP98106814.1

    申请日：1998-04-15

    申请人： NEC CORPORATION

    发明人： Ogawa, Tadahiko

    IPC分类号： H03K3/356

    CPC分类号： H03K3/356156 ,  H03K3/356173 ,  H03K3/35625

    摘要： A latch circuit (X, Y) for eliminating slew current flowing in between power sources during period when clock signal changes. In the latch circuit(X, Y), an input terminal is formed in such a way that dual transfer gates are connected to respective nodes remaining differential signal of bistable circuit which is constituted that one pair of clocked · CMOS inverter is subjected to mesh connection. An output terminal of holding signal of latch circuit is drains of PMOS and NMOS transistors being adjacent to end terminal of power source, which transistors are member of the one pair of clocked · CMOS inverter. Gates of PMOS and NMOS transistors being adjacent to side of output terminal are taken to be input terminal of gate signal of the latch circuit. During period of sampling calculation, since there exists MOS transistor which is connected in series between power sources and which is sure to stand of OFF state, it is capable of cutting transient slew current flowing between power sources (91, 92).