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1.发明公开Interactive video on demand system using packet transmission via ATM network 失效交互式视频点播系统，分组传输在ATM通信线路
公开(公告)号：EP0738083A3
公开(公告)日：1998-09-09
申请号：EP96104623
申请日：1996-03-22
CPC分类号： H04N21/47202 , H04N7/17318 , H04N7/17336 , H04N21/2365 , H04N21/4347
摘要： In an interactive video-on-demand system, real-time programs are encoded as a transport stream including a plurality of transport stream packets. Some of the transport stream packets include timing signals indicating the real time of the program. The transport stream packets are formatted into transport cells for transport over an asynchronous transfer mode network from a source to a destination. The cells are transported at a transport rate which is determined by a network clock. The transport rate is chosen to deliver the transport stream faster than the real time of the program. While transporting the transport stream, it is determined if the transport stream is being transported ahead of the real time of the program. In this case, idle cells are injected into the transport stream to have the program arrive at the destination in the real time of the program.
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公开(公告)号：EP0582395A3
公开(公告)日：1998-04-01
申请号：EP93305508
申请日：1993-07-14
发明人： ABADI MARTIN , BURROWS MICHAEL , LAMPSON BUTLER
CPC分类号： H04L63/1441 , H04L9/0838 , H04L63/1466 , H04L2209/125 , H04L2209/34
摘要： In a computer network, each pair of host computers that need to exchange data packets establish a single host-to-host encryption/decryption key. Then, whenever one host computer sends a data packet to the other host computer, it first forms a predefined logical combination of the established host-to-host key and the destination buffer index to which the data packet is being sent, and then uses the resulting value to encrypt the secure portions of the data packet. The destination buffer index is included in the data packet's header, which is not encrypted. When the receiving host computer receives the encrypted data packet, it reads the destination buffer index from the packet header, forms the same predefined logical combination of the established host-to-host key and the destination buffer index to generate a decryption key, and uses the computed decryption key to decrypt the secure portions of the received data packet. If the destination buffer index in the received data packet has been modified either by noise or by an interloper, the decryption key computed by the receiving host computer will be different from the encryption key used by the sending host computer, and therefore the portions of the received data packet decrypted using the computed decryption key will be unintelligible. Thus, interlopers are prevented from breaching the confidentiality of encrypted data.
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公开(公告)号：EP0228369A4
公开(公告)日：1987-10-26
申请号：EP85903483
申请日：1985-06-12
发明人： HERTRICH FRIEDRICH R
IPC分类号： G03B1/02 , B65H75/38 , G11B15/67 , G11B23/26 , G03B1/04 , G03B1/56 , G03C1/76 , G03D13/10 , G11B15/00 , G11B15/32 , G11B17/00
摘要： The present arrangement includes a first tape leader (11) which can be readily and automatically coupled to a second tape leader (23). In a preferred embodiment the first tape leader is connected to be wound on a take up reel while the second tape leader is connected to a tape to be pulled from a supply reel. The first tape leader (11) has one end formed into a mushroom like tab (13) with a supporting stem (17). The second tape leader (23) has a locking aperture (21) at one end thereof which is proportioned so that a wide section thereof can fit over said mushroom like tab (13) while a narrow section thereof will accept the stem (17) but block passage of the mushroom tab (13) therethrough. Accordingly when the tab (13) is passed through the wide section and the leader (11) is moved (pulled) toward the narrow section of the locking aperture (21), the tab (13) and part of the stem (17) become locked in the narrow section. Hence the leaders are locked, or, buckled, to enable the first tape leader (11) to pull the second leader (23). The first and second tape leaders each have a smoothing aperture (25), (33) therein which provides a means to accept the bumps created by buckling the tab (13) into the locking aperture (21) so that the wrapped around leaders are in a smooth configuration when pulling a tape.
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4.发明公开Emitter coupled logic latch with boolean logic input gating network. 失效Verriegelungsschaltung in emittergekoppelter Logik e eem Eingangs-SchaltnetzwerkfürBoolesche Logik。
公开(公告)号：EP0206891A2
公开(公告)日：1986-12-30
申请号：EP86401214
申请日：1986-06-05
IPC分类号： H03K3/286 , H03K3/2885 , H03K19/086
CPC分类号： H03K19/0866 , H03K3/2885
摘要： A latch circuit including an input logic network that incorporates emitter-coupled logic switching arrangements connected in multiple levels to perform logical operations on the received input signals. The latch circuit is controlled by differential clock signals coupled to a differential switch circuit that is connected to the input logic network to form another switch level. An output buffer is connected to the input logic network to generate output signals of selected logic voltage levels. When the differential clock signals are in a pass condition, the input logic network is enabled to transmit an output signal to the output buffer. When the differential clock signals are in a latch, or hold, condition, the input logic network is disabled and a feedback network is enabled to maintain the signal to the output buffer in the conditions it was in when the differential clock signals changed conditions.
摘要翻译： 一种锁存电路，包括输入逻辑网络，该输入逻辑网络包含以多个级别连接的发射极耦合逻辑开关装置，以对所接收的输入信号执行逻辑运算。 锁存电路由耦合到差分开关电路的差分时钟信号控制，差分开关电路连接到输入逻辑网络以形成另一个开关电平。 输出缓冲器连接到输入逻辑网络以产生所选逻辑电压电平的输出信号。 当差分时钟信号处于通过状态时，输入逻辑网络使能将输出信号发送到输出缓冲器。 当差分时钟信号处于锁存或保持状态时，禁止输入逻辑网络，并且在差分时钟信号变化的条件下使反馈网络能够使信号保持在输出缓冲器中。
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公开(公告)号：EP0641104A3
公开(公告)日：1998-07-29
申请号：EP94203074
申请日：1989-03-03
IPC分类号： G06F15/16 , G06F15/177 , H04L29/00 , H04L29/06 , H04L12/00
摘要： A message transfer arrangement includes a client node and a server node interconnected by a data link. The client node sequentially receives requests from user applications and generates, in response to each request, command messages for transmission by said interface, each command message including a command and having a transmit slot identifier identifying the request in the sequence of requests received by said request receiver and a transmit sequence identifier identifying the command message in the sequence of command messages relating to the request. The selection of whether to transmit a command message related to one request or to a subsequent request is based on a received slot identifier and a received sequence identifier in a response message.
The server node receives command messages from, and transmits response messages to, the client node over the data link. It selectively executes the command contained in each command message and generates, in response thereto, a response message including a response slot identifier and response sequence identifier corresponding to the command slot identifier and command sequence identifier. The determination of whether to execute a command in a command message is based on the command slot identifier and command sequence identifier of the received command message received by interface and the command slot identifer and command sequence identifier of the command message containing the previously executed command.-
6.发明公开Register and instruction controller for superscalar processor 失效注册和Befehlssteuerungfüreinen superskalaren Prozessor
公开(公告)号：EP0767425A3
公开(公告)日：1998-07-08
申请号：EP96307288
申请日：1996-10-04
发明人： JOUPPI NORMAN PAUL
CPC分类号： G06F9/3855 , G06F9/3012 , G06F9/3824 , G06F9/3826 , G06F9/3828 , G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3885 , G06F9/3891
摘要： In a superscalar computer system, a plurality of instructions are executed concurrently. The instructions being executed access data stored at addresses of the superscalar computer system. An instruction generator, such as a compiler, partitions the instructions into a plurality of sets. The plurality of sets are disjoint according to the addresses of the data to be accessed by the instructions while executing in the superscalar computer system. The system includes a plurality of clusters for executing the instructions. There is one cluster for each one of the plurality of sets of instructions. Each set of instructions is distributed to the plurality of clusters so that the addresses of the data accessed by the instructions are substantially disjoint among the clusters while immediately executing the instructions. This partitioning and distributing minimizes the number of interconnects between the clusters of the superscalar computer.
摘要翻译： 在超标量计算机系统中，同时执行多个指令。 正在执行的指令访问存储在超标量计算机系统的地址处的数据。 诸如编译器的指令生成器将指令分成多个集合。 根据在超标量计算机系统中执行时由指令访问的数据的地址，多个集合是不相交的。 该系统包括用于执行指令的多个簇。 对于多组指令中的每一组，存在一个集群。 每组指令被分配到多个簇，使得由指令访问的数据的地址在立即执行指令之间在簇之间基本上不相交。 这种分配和分发使超标量计算机的集群之间的互连数量最小化。
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公开(公告)号：EP0770982A3
公开(公告)日：1997-12-29
申请号：EP96116308
申请日：1996-10-11
发明人： THACKER CHARLES P
IPC分类号： G09G5/12
CPC分类号： G09G5/12
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8.发明公开DATENVERARBEITUNGSSYSTEM UND VERFAHREN ZU SEINER STEUERUNG SOWIE CPU-PLATINE. 失效数据处理系统和控制与CPU BOARD FOR过程。
公开(公告)号：EP0439591A1
公开(公告)日：1991-08-07
申请号：EP90912691
申请日：1990-08-23
发明人： SCHLAGE THOMAS
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Dans un système de traitement des données comportant une unité centrale, une mémoire principale (2) et un bus de système (3) pouvant être relié à la mémoire principale (2) et à différentes autres unités fonctionnelles, la mémoire principale (2) peut être reliée directement à l'unité centrale (1) et il est prévu un premier dispositif de commutation (5), qui commande la liaison entre l'unité centrale (1) et la mémoire principale (2), et un deuxième dispositif de commutation (7), qui commande la liaison entre le bus de système (3) et la mémoire prinicpale (2), le premier et le deuxième dispositif de commutatiion (5, 7) étant reliés entre eux de telle manière que l'un seulement des deux dispositif puisse libérer la liaison de l'unité centrale (1) ou celle du bus de système (3) avec la mémoire principale. La mémoire principale, le premier et le deuxième dispositif de commutation ainsi que la première et la deuxième mémoire tampon sont disposés sur la même carte que l'unité centrale (1).
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公开(公告)号：EP0229052A4
公开(公告)日：1987-10-22
申请号：EP85903484
申请日：1985-06-12
发明人： HERTRICH FRIEDRICH R
摘要： An elongated member (11) which has a finger like protrusion (13) and a cam protrusion (15) both of which are disposed close to one end thereof. The elongated member has an elongated slot at one end which fits over a stud (19) and is further rotationally coupled to a crank (21) so that the elongated member can pivot around said stud in a number of different positions in response to the crank being moved. The crank is rotationally coupled to a cam follower (17) and the crank is further arranged to rotate about a stud (25). When a tape leader (27) from a take up reel is to be joined to a tape leader from a supply reel, the elongated member is moved toward the tape leader from the take up reel and the finger like protrusion (15) enters a first slot in the take up reel leader and moves that leader to an extended position whereat the cam protrusion (in a preferred embodiment) cams a tab (41) on the end of the take up reel leader away from the elongated member. The tab (41) is formed to have a stem section. Thereafter, the housing for the supply reel is moved toward the joining mechanism. The supply leader which is extended from the housing has a locking slot (39) therein which has a first section which fits over the tab. As the housing continues to move toward the joining mechanism it moves the cam follower which is part of the joining mechanism. In response to said camming action, the follower is partially rotated and partially linearly moved. In response to the further moving of the cam follower, the elongated member moves said finger like protrusion out of said first slot and the two leaders are joined, or buckled, to be used for pulling tape from the supply reel onto the take up reel.
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公开(公告)号：EP0090040A4
公开(公告)日：1986-01-28
申请号：EP82903413
申请日：1982-10-04
CPC分类号： G11B20/1883 , G11B20/1252 , G11B20/1803 , G11B2220/20 , G11B2220/2508
摘要： In a disk type mass storage facility for data processing systems, a disk format which improves handling of defective segments of medium and reduces access time. The format has three layers. A first, physical layer comprises the bytes, sectors and collections of sectors, as well as error detection and correction codes. A second, logical layer is used to address the physical layer and to collect together sectors to form multiplicity of separately addressable spaces, with space having a distinct functional utility. As a third, functional layer the use of data fields in each space is specified. This layer governs the handling of bad blocks if required, and the use of certain format information. At the physical layer, bits are collected into sectors, sectors are collected into tracks, tracks are collected into groups, and groups are collected into cylinders. These are logically, rather than physically, defined collections. A group is set of tracks wherein individual tracks in a group can be selected in the inter-sector rotation time. At the logical layer, the disk is divided into three main areas, each separately addressable. The first main area is broken down into two sub-areas. The first sub-area (12) is available to the host computing system for its use; the second sub-area (14 and 16) is used for replacement of the bad blocks. The second is for format information. The third main area (18) is for diagnostics. Handling of bad blocks is controlled by a hierarchically layered process. A portion of each disk, distributed across the medium, is reserved as spare sectors to replace defective sectors. After a bad sector is replaced, future attempts to the replacement sector. For the simplest revectoring, the bad block is replaced by a replacement block in a known location. If that cannot be done, multiple copies of the replacement block's header are stored in the bad block's data field and the copies are compared to find the replacement address. If the comparison fails, or the header cannot be read, a back-up table is available to match the available replacement addresses with the original address which was replaced. A special code is used to identify blocks wherein the medium is good but the contents of the block are logically corrupted.
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