公开(公告)号：EP0221425A3

公开(公告)日：1990-04-04

申请号：EP86114437.6

申请日：1986-10-17

申请人： GENERAL ELECTRIC COMPANY

发明人： Sutcliffe, Patrick Lee

IPC分类号： G06F7/552

CPC分类号： G06F7/5525

摘要： Circuitry for computing the square root of a number wherein the input number is partitioned into digit pairs left and right of the radix point. Pairs of zeros are added after the radix point for each digit of the desired precision. The most significant zero digit pairs are skipped to the first digit pair which is not zero, accordingly the first answer bit is a 1. A residue is formed by subtracting the 1 from the digit pair, multiplying by 4, and adding the next most significant digit pair. The procedure is repeated for subsequent bit pairs by defining trial divisors and determining residue values.

公开(公告)号：EP0251702A3

公开(公告)日：1989-01-04

申请号：EP87305659.2

申请日：1987-06-25

申请人： RCA LICENSING CORPORATION

发明人： Muterspaugh, Max Ward

IPC分类号： H03D7/12

CPC分类号： H03D7/12

摘要： A mixer for mixing first and second signals for providing a difference signal comprises a mixing transistor (200). The first and second signals are applied between the base and emitter electrodes of the transistor. A non-linear impedance (212) is coupled in series with the emitter electrode. Spurious signal components are reduced in amplitude compared with the difference signal.

公开(公告)号：EP0265554A1

公开(公告)日：1988-05-04

申请号：EP86115146.2

申请日：1986-10-31

申请人： INTERSIL, INC. (a Delaware corp.)

发明人： Wei, James Yuan

IPC分类号： H03K19/177

CPC分类号： H03K19/1776 ,  G11C16/0433 ,  H03K19/17712

摘要： Disclosed is a programmable logic gate array employing a plurality of reprogrammable fuses (20) having a logical NAND characteristic for logically connecting selected inputs (A o -A n ) to selected logic gates (22). Means E 5 , P s are also disclosed for programming said fuses and for providing appropriate signals to allow three modes of operation of the logic gate array; programming, erasure and normal logic operation.

摘要翻译： 公开了一种可编程逻辑门阵列，其采用具有逻辑NAND特性的多个可重新编程熔丝（20），用于将所选输入（A o-A n）逻辑连接到所选逻辑门（22）。 还公开了装置E5，Ps，用于对所述保险丝进行编程，并提供适当的信号以允许逻辑门阵列的三种操作模式; 编程，擦除和正常逻辑运算。

公开(公告)号：EP0219287A1

公开(公告)日：1987-04-22

申请号：EP86307675.8

申请日：1986-10-03

申请人： RCA LICENSING CORPORATION

发明人： Haferl, Peter Eduard

IPC分类号： H04N9/29

CPC分类号： H04N9/29

摘要： A degaussing circuit for a cathode ray tube of a video display apparatus includes a resonating capacitor (C1) that is charged prior to degaussing. A degaussing coil (L DG ) is disposed about the cathode ray tube. An SCR (SCR1), responsive to an on/off control signal, is turned on by a control switch (Q1) for coupling the resonating capacitor (C1) to the degaussing coil (L DG ) in order to generate an AC degaussing current in the coil having an amplitude that diminishes to a low amplitude during a degaussing interval. Positive feedback (R2,C2) is used for speeding up the turn-on time of the control switch (Q1). A series pass transistor switch (Q2) couples a source (T1 or 51) of a supply voltage (VUR1) to a delay network (R7,C5). The series pass transistor switch (Q2) is coupled in the current path of the current that is supplied by the power supply. An energizing voltage (V Q ₂) is developed at the output of the delay network (R7,C5). The magnitude of the energizing voltage exceeds a predetermined value after a predetermined delay time following conduction of the transistor switch (Q2), that is determined by the delay network. The delayed energizing voltage is coupled to a deflection circuit (56,57,58) to initiate deflection circuit operation after conclusion of the degaussing.

公开(公告)号：EP0209313A2

公开(公告)日：1987-01-21

申请号：EP86305273.4

申请日：1986-07-08

申请人： RCA CORPORATION

发明人： Ott, Russell George

IPC分类号： H03K21/18

CPC分类号： G04G7/00 ,  H03K21/18

摘要： A timing system (Fig. 1) ordinarily includes: a timer circuit (24), a source (11, 14) of first clock pulses for advancing the timer circuit, and a circuit (16, 18) for reading out the timer circeit in delayed synchronizism with the clock pulses. In order to allow the timer circuit to be advanced by second clock pulses from a second source (29), where the second clock pulses are asynchronous with respect to the first clock pulses, there is provided a synchronizing or storage circuit (32) for storing an indication of the occurrence of each second clock source pulse. The timer circuit is advanced only when there are present the stored indication and the next-occurring first clock pulse. The stored indication thereafter is erased, in anticipation of receipt of the next-occurring second clock pulse.

公开(公告)号：EP0192336A1

公开(公告)日：1986-08-27

申请号：EP86300411.5

申请日：1986-01-21

申请人： RCA CORPORATION

发明人： Chang, Kern Ko Nan

IPC分类号： H01J29/02 ,  H01J29/58

CPC分类号： H01J29/563 ,  H01J29/80

摘要： The cathode-ray tube (10) includes a faceplate panel (12) and an electron gun (14), adapted to emit a beam of electrons for striking a cathodoluminescent screen (16) disposed on the panel. It has a conductive loop (28) disposed around the perimeter of the screen for locally altering the trajectory of the electron beam adjacent the perimeter, thereby achieving a focusing effect for reducing the size of cathodoluminescent spots adjacent the perimeter of the screen. The conductive loop has a significantly lower voltage applied thereto than to the screen.

摘要翻译： 阴极射线管（10）包括面板（12）和电子枪（14），适于发射用于击打设置在面板上的阴极发光屏（16）的电子束。 它具有围绕屏幕的周边设置的导电回路（28），用于局部地改变邻近周边的电子束的轨迹，从而实现用于减小邻近屏幕周边的阴极发光点的尺寸的聚焦效果。 与屏幕相比，导电环路施加的电压明显较低。

公开(公告)号：EP0178857A2

公开(公告)日：1986-04-23

申请号：EP85307284.1

申请日：1985-10-11

申请人： RCA LICENSING CORPORATION

发明人： Chen, Hsing-Yao

IPC分类号： H01J29/50

CPC分类号： H01J29/503 ,  H01J2229/4841 ,  H01J2229/4865 ,  H01J2229/4872

摘要： An inline electron gun (26:26') for a cathode-ray tube (8) includes an improved beam forming region comprising three cathodes (34), a control grid (36) and a novel screen grid electrode means (38, 38'), the latter comprising two spaced apart metal members (G2a, G2b;G2a',G2b'). In one embodiment (26), the first member (G2a) closest to the control grid is relatively thick and has three slots (52) formed in one surface thereof facing away from the control grid. Circular apertures (54) are formed within the slots and extend through the body of the first member. The second member (G2b) has three circular apertures (56) therethrough aligned with the circular apertures in the first member. When a dynamic signal is superimposed on the DC bias voltage and applied to the second member, the first member shields the control grid from the dynamic signal so that little or no brightness modulation occurs. In a second embodiment (26'), the first (G2a') and second (G2b') members of the screen grid (38') are structurally interchanged. In a third embodiment, the first (G2a) and the second (G2b) members have orthogonally disposed rectangular slots formed in facing surfaces.

摘要翻译： 用于阴极射线管（8）的直列式电子枪（26:26'）包括改进的射束形成区域，该射束形成区域包括三个阴极（34），控制栅极（36）和新颖的栅格栅极电极装置（38,38' ），后者包括两个间隔开的金属构件（G2a，G2b; G2a'，G2b'）。 在一个实施例（26）中，最接近控制栅格的第一构件（G2a）相对较厚并且具有形成在其背离控制栅格的一个表面中的三个狭槽（52）。 圆形孔（54）形成在槽内并延伸穿过第一构件的主体。 第二构件（G2b）具有三个与第一构件中的圆形孔对齐的圆形孔（56）。 当动态信号叠加在直流偏置电压上并施加到第二部件上时，第一部件将控制栅极与动态信号隔离开，使得很少或不发生亮度调制。 在第二实施例（26'）中，筛网（38'）的第一（G2a'）和第二（G2b'）构件在结构上互换。 在第三实施例中，第一（G2a）和第二（G2b）构件具有在相对表面中形成的正交设置的矩形槽。

公开(公告)号：EP0163514A1

公开(公告)日：1985-12-04

申请号：EP85303729.9

申请日：1985-05-28

申请人： RCA LICENSING CORPORATION

发明人： Willis, Donald Henry ,  Christopher, Todd J.

IPC分类号： H04N5/44

CPC分类号： H04N7/012

摘要： Phase detectors (202, 204) in a progressively scanned television receiver measure the phase of the receiver video speed-up memory read (8 fsc ) and write (4 fsc ) clocks with respectto the double line-rate horizontal sweep signal (FB) of the display. Delay means (34, 36) are provided for delaying the video signal recovered from the memory (30, 32) as a function of the difference (224) between the read and write clock phase measurements each time the memory is read. The delay is effective for minimizing visible artifacts which otherwise may tend to occur when displaying "non-standard" video signals wherein the ratio of the color- subcarrier frequency to the line-frequency of the incoming video signal differs from a given broadcasting standard.

摘要翻译： 逐步扫描的电视接收机中的相位检测器（202,204）测量接收机视频加速存储器读取（8fsc）的相位和相对于双线速率水平扫描信号（FB）的写入（4fsc）时钟 显示。 提供延迟装置（34,36），用于在每次读取存储器时读取和写入时钟相位测量值之间的差值（224）延迟从存储器（30,32）恢复的视频信号。 当显示“输入视频信号的彩色副载波频率与输入视频信号的频率之间的比率”与给定的广播标准不同时显示“非标准”视频信号时，该延迟对于最小化可能会发生倾斜的可见伪影是有效的。

公开(公告)号：EP0147981A1

公开(公告)日：1985-07-10

申请号：EP84308661.2

申请日：1984-12-13

申请人： RCA LICENSING CORPORATION

发明人： Hettiger, James

IPC分类号： H03K5/00 ,  H04N9/44

CPC分类号： H04N9/44

摘要： In a color TV receiver incorporating automatic kinescope bias (AKB) control circuits, a first train (rb) of monolevel pulses with timing suitable for retrace blanking purposes and a second train (bg) of monolevel pulses with "backporch" timing appropriate for burst gating purposes are applied to a circuit serving to generate at a first terminal (P) a train of bilevel pulses exhibiting a first voltage level during periods of overlapping of the pulses of the first and second trains, and exhibiting a second, lesser voltage level during the remaining, non-overlapping portions of the pulses of the first train. A resistor (30) interconnects the first terminal with a second terminal (J). A keyed voltage source (33), responsive to a third train (a) of monolevel pulses timed to indicate recurring kinescope bias control intervals, develops a voltage of a third level, intermediate the first and second voltage levels, at the second terminal during-the recurring control intervals. The keyed voltage source exhibits, during the control intervals, an output impedance significantly lower than the impedance exhibited by the interconnecting resistor (30). During periods intervening successive ones of the control intervals, the voltage source is effectively disabled and exhibits an output impedance significantly higher than the impedance exhibited by the resistor.

公开(公告)号：EP0100679A1

公开(公告)日：1984-02-15

申请号：EP83304459.7

申请日：1983-08-02

申请人： RCA CORPORATION

发明人： Lewis, Henry Garton, Jr. ,  Balaban, Alvin Reuben ,  Bolger, Thomas Vincent ,  Steckler, Steven Alan

IPC分类号： H04N9/64 ,  H04N11/06 ,  H03H15/00

CPC分类号： H04N9/78

摘要： The signal separation system operating at a reduced data rate requires comparably fewer storage locations than previous arrangements. Such a signal separation system, for use in a television receiver, separates two sampled data video signal components which are interleaved in frequency. This system comprises means (12) for passing the sampled data video signal at a data rate less than the original sampling rate. A comb filter (20) is responsive to the reduced sample rate signal, and produces the comb-filtered output signal.

摘要翻译： 以较低的数据速率运行的信号分离系统需要与之前的布置相比较少的存储位置。 用于电视接收机的这种信号分离系统分离频率交错的两个采样数据视频信号分量。 该系统包括用于以低于原始采样率的数据速率传送采样数据视频信号的装置（12）。 梳状滤波器（20）响应于降低的采样率信号，并产生梳状滤波的输出信号。