公开(公告)号：EP0700599A1

公开(公告)日：1996-03-13

申请号：EP95910702.0

申请日：1995-03-17

Applicant: PHILIPS ELECTRONICS N.V. ,  PHILIPS NORDEN AB

Inventor： MARTIN, Brian

IPC: H03K19

CPC classification number: H03K19/00384

Abstract: An inverter includes a series arrangement of a first PFET and a first NFET between Vdd and ground. The first FETs have their gates connected to one another and to the input. The inverter has a first switching threshold. A series arrangement of second and third PFETs is connected in parallel to the first PFET. The second and third PFETs are connected to Vdd and the inverter's output, respectively. A further inverter with a second switching threshold is connected to the input to control the second PFET in response to the input signal. The third PFET is controlled in parallel to the first PFET. The switching threshold of the compound circuit is substantially constant over a wide range of Vdd levels.

公开(公告)号：EP0698273A1

公开(公告)日：1996-02-28

申请号：EP95907132.0

申请日：1995-02-15

Applicant: Philips Electronics N.V.

Inventor： SACHDEV, Manoj

IPC: G01R31 ,  G11C8 ,  G11C29

CPC classification number: G11C29/50 ,  G11C8/04 ,  G11C8/12 ,  G11C11/41 ,  G11C29/34 ,  G11C2029/5006

Abstract: An SRAM has a plurality of respective memory cells coupled to a respective one of a plurality of word lines and to a pair of bit lines. The SRAM comprises IDDQ test means to render the word lines active in parallel by cumulatively increasing a number of active ones among the word lines. This permits the writing of a specific logic state in all cells of a column through the tiny bit line drivers that are progressively assisted by the cells already written, thus avoiding the use of additional heavy write circuitry for IDDQ test purposes only.

公开(公告)号：EP0728343A1

公开(公告)日：1996-08-28

申请号：EP95925100.0

申请日：1995-08-02

Applicant: PHILIPS ELECTRONICS N.V.

Inventor： HAISMA, Jan ,  WIDDERSHOVEN, Franciscus, Petrus ,  COLLET, Marnix, Guillaume

IPC: G06T17 ,  G06T3 ,  G06T5 ,  G06T7

CPC classification number: G06T5/00 ,  H04N5/262

Abstract: An image processing system creates a two-dimensional output image with enhanced depth sensation by operating on a two-dimensional input image. The system processes the input image non-uniformly by selecting an area in the input image according to a predetermined criterion, and changing a property, e.g., its brightness, of the area relative to a corresponding property of a complement of the area in the input image.

公开(公告)号：EP0717851A1

公开(公告)日：1996-06-26

申请号：EP95921948.0

申请日：1995-06-29

Applicant: PHILIPS ELECTRONICS N.V.

Inventor： SACHDEV, Manoj

IPC: G01R31 ,  G06F11 ,  H03K3

CPC classification number: G06F11/2236 ,  G01R31/3004 ,  G01R31/3008 ,  G01R31/318541 ,  G01R31/318577

Abstract: A flipflop has master and slave interconnected through a buffer. The master has its inverters located outside the signal path from input to output, as the buffer provides the driving capability required for both IDDQ-testing and operational use. This configuration enables IDDQ-testing without further circuitry added to the flipflop and reduces propagation delay in the signal path.

公开(公告)号：EP0693195A1

公开(公告)日：1996-01-24

申请号：EP95905736.0

申请日：1995-01-27

Applicant: PHILIPS ELECTRONICS N.V.

Inventor： DE LANGE, Alphonsius, Anthonius, Jozef

IPC: G06T1 ,  G06F13 ,  G06F15

CPC classification number: G06F15/17

Abstract: A data processing system comprises a plurality of processing elements being operative to process data and being coupled in parallel to a bus via a control means that governs data communication. The control means comprises a plurality of buffer means, and each respective one of the buffer means includes a respective plurality of parallel buffer segments. The control means is operative to selectively connect a single one of the buffer segments in respective ones of the buffer means to respective ones of the processing elements. This effectively permits distributing of the data in an arbitrary manner over the elements by sorting the data in advance in the segments according to destination. The system is highly suitable to handle video and graphics data in image synthesis.

公开(公告)号：EP0744053A1

公开(公告)日：1996-11-27

申请号：EP94931667.0

申请日：1994-11-21

Applicant: Philips Electronics N.V.

Inventor： BUIJ, Arnold, Willem ,  BEIJ, Marcel

IPC: G06F13 ,  G06F12 ,  H04L12 ,  H04L29

CPC classification number: H04L29/12254 ,  G06F12/0661 ,  G06F12/0684 ,  H04L29/1232 ,  H04L61/2038 ,  H04L61/2092

Abstract: A control system comprises modules, and control means to control assignment of addresses to the modules. Each particular module has a particular number. The control means iteratively determines which one of the modules has an extreme one among the particular numbers. Each module is stimulated to conditionally respond if its particular number lies within a certain range. The range is altered until the module with the extreme is found. This process is repeated for the next lower extreme until all modules have been validated. Addresses are then created and stored in the modules for access during operational use.

公开(公告)号：EP0722582A1

公开(公告)日：1996-07-24

申请号：EP95921947.0

申请日：1995-06-29

Applicant: Philips Electronics N.V.

Inventor： MEIJER, Peter, Bartus, Leonard

IPC: G06F1 ,  G06F7 ,  G06F17

CPC classification number: G06F17/5009 ,  G06F1/03 ,  G06F17/13

Abstract: A signal generator implements a dynamic behaviour described by differential equations specifying a predetermined functional relationship. The generator includes a mapping section for mapping inputs onto outputs according to a mathematical correspondence, differentiating means at selective ones of the inputs for providing time-derivatives, and a feedback path for selectively coupling outputs to inputs, either directly or via the differentiating means. The feedback path and differentiating means constrain the mapping and establish aforesaid relationship.

公开(公告)号：EP0711447A1

公开(公告)日：1996-05-15

申请号：EP95915990.0

申请日：1995-05-09

Applicant: Philips Electronics N.V.

Inventor： SHIMANEK, Schuyler ,  ANDERSON, Alma

IPC: G01R31 ,  G11C17 ,  G11C29 ,  H01L21 ,  H03K19

CPC classification number: G11C17/16 ,  G11C29/44

Abstract: A PLD with an array of fuse or anti-fuse links includes verification circuitry configured to classify the links into three zones, corresponding to a 'closed' state zone of low resistance values, an 'open' state zone of high resistance values and a 'forbidden' state zone intermediate the 'closed' and 'open' state zones. Because the ratio between the higher and lower resistance value is typically 200, the verification circuitry includes a switchable two level current source that produces a voltage across the link of correct dynamic range.

公开(公告)号：EP0704078A1

公开(公告)日：1996-04-03

申请号：EP95909927.0

申请日：1995-03-13

Applicant: PHILIPS ELECTRONICS N.V.

Inventor： MAKINWA, Kofi, Afolabi, Anthony ,  VAN BEEK, Jan, Erik ,  GROOTEN, Marcellinus, Arnoldus, Maria

IPC: G06F3 ,  G06K11

Abstract: A graphical tablet and a stylus interact electromagnetically with one another. The stylus includes a coil and a transducer to affect an inductance of the coil in response to a force exerted on a tip of the stylus. The transducer comprises first and second ferrite cores. The cores are mounted to move with respect to one another in response to the force. The cores are in contact with one another in the absence of the force. Disengaging causes a well detectable jump in the inductance.

Abstract translation: 图形平板和手写笔相互电磁相互作用。 触针包括线圈和换能器，以响应施加在触针尖端上的力而影响线圈的电感。 换能器包括第一和第二铁氧体磁芯。 芯体响应于力而安装成相对于彼此移动。 在没有力的情况下，芯部彼此接触。 分离引起电感中可检测到的跳跃。