公开(公告)号：EP1830366A4

公开(公告)日：2009-11-11

申请号：EP04807686

申请日：2004-12-24

Applicant: SPANSION JAPAN LTD ,  SPANSION LLC

Inventor： FURUYAMA TAKAAKI ,  KATO KENTA

IPC: G11C29/00 ,  G11C16/02

CPC classification number: G11C29/1201 ,  G11C5/14 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  G11C29/50004 ,  G11C29/82 ,  G11C2029/5006

公开(公告)号：EP1606824B1

公开(公告)日：2007-06-06

申请号：EP04716681.4

申请日：2004-03-03

Applicant: Koninklijke Philips Electronics N.V.

Inventor： PINEDA DE GYVEZ, Jose, D., J. ,  SACHDEV, Manoj ,  PAVLOV, Andrei

IPC: G11C29/00

CPC classification number: G11C29/50 ,  G11C11/41 ,  G11C2029/5006

Abstract: A method and apparatus for testing a static random access memory (SRAM) array for the presence of weak defects. A 0/1 ratio is first written to the memory array (step 100), following which the bit lines BL and BLB are pre-charged and equalized to a threshold detection voltage (step 102). The threshold detection voltage is programmed according to the 0/1 ratio of cells, so as to take into account specific cell criterion and/or characteristics. Next, the word lines associated with all of the cells in the array are enabled substantially simultaneously (step 104), the bit lines are then shorted together (step 106), the word lines are disabled (step 108) and the bit lines are released (step 110). Following these steps, the contents of the SRAM array are read and compared against the original 0/1 ratio (step 112). 10 Any cells whose contents do not match the original 0/1 ratio (i.e. those whose contents have flipped) are marked or otherwise identified as 'weak' (step 114).

公开(公告)号：EP1774531A2

公开(公告)日：2007-04-18

申请号：EP05778107.2

申请日：2005-08-02

Applicant: Analog Devices, Inc.

Inventor： BRENNAN, Oliver ,  DOYLE, Denis

IPC: G11C17/00 ,  G11C17/18

CPC classification number: G11C29/027 ,  G11C17/14 ,  G11C17/16 ,  G11C17/18 ,  G11C29/50 ,  G11C2029/5006

Abstract: A programmable read only memory includes a matrix of semi-fusible link memory cells, each including a semi-fusible link having an intact impedance and a blown impedance; a bit line voltage supply switching circuit for applying a current to at least one selected bit line; a word line address decoder for selecting a word line; and a program control logic circuit for blowing the semi-fusible links in the memory cells identified by the intersection of the selected word and bit lines; a method is disclosed of testing programmed and unprogrammed read only memory.

公开(公告)号：EP0933785B1

公开(公告)日：2001-12-12

申请号：EP99105456.0

申请日：1994-02-08

Applicant: FUJITSU LIMITED

Inventor： Kumakura, Sinsuke Fujitsu Limited ,  Yamazaki, Hirokazu Fujitsu Limited ,  Watanabe, Hisayoshi Fujitsu Limited ,  Kasa, Yasushi Fujitsu Limited

IPC: G11C29/00 ,  G11C5/14 ,  G11C11/407

CPC classification number: G11C29/021 ,  G11C5/14 ,  G11C5/143 ,  G11C7/062 ,  G11C16/04 ,  G11C29/02 ,  G11C29/24 ,  G11C29/44 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50016 ,  G11C2029/5006

Abstract: An object of the present invention is to provide a semiconductor device that permits easy and efficient testing. A nonvolatile semiconductor memory comprises word lines WLi and bit lines BLi, a memory cell matrix 17 consisting of nonvolatile memory cells Cij, a sense amplifier 15, a write/erase timing circuit 9 for performing timing control necessary for write and erase operations, and a status register 2 for storing the operating state of the memory at the completion of the operation of the circuit 9, wherein there are provided, outside the address of the memory cell matrix 17, two kinds of dummy cells, D1, D2, D3,..., whose values are fixed to different values that induce different outputs from the sense amplifier 15. A pass condition or a fail condition is generated by accessing the dummy cells.

公开(公告)号：EP0770207A4

公开(公告)日：1999-10-13

申请号：EP95924076

申请日：1995-06-26

Applicant: BULL BRIAN S

Inventor： BULL BRIAN S

IPC: G01N15/05

CPC classification number: G01N15/05 ,  G11C16/04 ,  G11C2029/5002 ,  G11C2029/5006

Abstract: An apparatus and method for rapid determination of erythrocyte sedimentation rates for a blood specimen (29) which can be linearly transposed to Westergren sedimentation rates. The method includes the steps of inducing accelerated rouleaux formation in the specimen (29) in an amount sufficient to begin settling at substantially the decantation rate for the specimen. In one embodiment a structure (27) which produces a very thin cross-sectional region (37) of the specimen (29) inside the lumen (23) of a specimen container (21) is provided to accelerate rouleaux formation. In an alternative embodiment (120), accelerated rouleaux formation is accomplished using a centrifuge (122). A third embodiment employs a movable rod (223) mounted inside the specimen tube (221) to induce accelerated rouleaux formation. All embodiments of the process next employ gravity settling the specimen in a near horizontal oriented container (21, 121, 221). Thereafter, the amount of settling occurring is determined. A sealed specimen container (21, 121, 221) which permits thorough mixing of blood in a very small diameter container for use in performing the method also is provided.

公开(公告)号：EP0856188A2

公开(公告)日：1998-08-05

申请号：EP96929800.0

申请日：1996-08-30

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： TANG, Yuan

IPC: G11C16 ,  G11C29

CPC classification number: G11C16/3477 ,  G11C16/04 ,  G11C16/28 ,  G11C16/3468 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50004 ,  G11C2029/5006

Abstract: A memory device including an array of cells, where a reference current is generated by a predetermined number of reference cells disposed separate from the array of cells, the transconductance of such reference cells being equal to the transconductance of the cells of the array.

公开(公告)号：EP0642137A3

公开(公告)日：1997-11-12

申请号：EP94202481.1

申请日：1994-08-31

Applicant: PHILIPS ELECTRONICS N.V.

Inventor： Sachdev, Mamoj, c/o Int, Octrooibureau B.V.

IPC: G11C29/00

CPC classification number: G11C29/50016 ,  G11C11/401 ,  G11C11/41 ,  G11C29/34 ,  G11C29/50 ,  G11C2029/5006

Abstract: An electronic circuit includes an array of a plurality of memory cells that are functionally organized in rows and columns. The circuit comprises test means that are selectively operative to access all cells of the array in parallel. An I DDQ -test then discovers whether or not there is a defect in any of the cells.

Abstract translation: 电子电路包括以行和列功能性组织的多个存储器单元的阵列。 该电路包括测试装置，其可选择性地操作以并行访问阵列的所有单元。 然后，IDDQ-测试发现是否在任何单元中存在缺陷。

公开(公告)号：EP0718850A1

公开(公告)日：1996-06-26

申请号：EP95402815.5

申请日：1995-12-14

Applicant: SGS-THOMSON MICROELECTRONICS S.A.

Inventor： Mirabel, Jean-Michel ,  Yero, Emilio

IPC: G11C29/00

CPC classification number: G11C29/50 ,  G11C16/04 ,  G11C2029/5006

Abstract: Une mémoire en circuit intégré qui comporte un dispositif de précharge et lecture des lignes de bit comprenant un élément de précharge (4), un convertisseur courant-tension (5) et un circuit de lecture (6), comprend en outre un circuit de test pour isoler la sortie du convertisseur de l'élément de précharge (13, DMA 1 ) et du circuit de lecture (14, DMA 2 ), pour appliquer une tension de test sur une cellule de la mémoire via le convertisseur et mesurer le courant dans la cellule.

Abstract translation: 存储器电路包括预加载元件（4），电流 - 电压转换器（5）和读取器电路（6）。 相关行（li）的选择激活预加载元件并将转换器输入（E）连接到线路。 转换器输出（S）连接到预加载元件和读取器电路输入。 存储器包括用于将转换器输出与预载元件（13，DMA1）和读取器电路（14，DMA2）隔离的测试电路。 它对转换器的输出端施加一个测试电压（Vtest），并测量该输出端的电流。 测试电路可以包括由测试信号（DMA）控制以切割读取器电路逻辑电源（Vcc）的晶体管（14）。

公开(公告)号：EP0686979A1

公开(公告)日：1995-12-13

申请号：EP94830283.1

申请日：1994-06-10

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Campardo, Giovanni ,  Camerlenghi, Emilio

IPC: G11C29/00 ,  G11C16/06 ,  G06F11/20

CPC classification number: G11C29/82 ,  G06F2201/81 ,  G11C16/04 ,  G11C16/34 ,  G11C29/50 ,  G11C2029/5006

Abstract: Since fault phenomena such as lowering of the cell gain and cell emptying occur during normal operation the present invention proposes that in the memory device the row and/or column address decoding means (RDEC,CDEC) comprise at least one non-volatile memory (NVM) for address mapping and that the reading and writing control logic (CL) comprise means (TST) designed to identify cell faults in the rows and/or columns of the matrix (MAT) of the memory device and writing means (WM) designed to write on said non-volatile memory (NVM) during normal operation addresses corresponding to redundant rows and/or columns (RID) present in the matrix (MAT) to rectify said faults.

Abstract translation: 由于在正常操作期间发生诸如电池增益降低和电池排空之类的故障现象，本发明提出在存储器件中，行和/或列地址解码装置（RDEC，CDEC）包括至少一个非易失性存储器（NVM ），并且读和写控制逻辑（CL）包括被设计用于识别存储器件的矩阵（MAT）的行和/或列中的单元故障的装置（TST）和写入装置（WM），其被设计为 在对应于存在于矩阵（MAT）中的冗余行和/或列（RID）的正常操作地址期间在所述非易失性存储器（NVM）上写入以校正所述故障。

公开(公告)号：EP0542856B1

公开(公告)日：1994-10-12

申请号：EP91914855.1

申请日：1991-08-06

Applicant: SGS-THOMSON MICROELECTRONICS S.A.

Inventor： GAULTIER, Jean-Marie ,  SILVESTRE DE FERRON, Gérard ,  GASTALDI, Roberto

IPC: G11C16/06 ,  G11C29/00 ,  G11C7/00

CPC classification number: G11C16/28 ,  G11C16/04 ,  G11C29/50 ,  G11C2029/5006

Abstract: Integrated circuit memories, and specifically electrically programmable memories, are described. In order to take into account the fact that memory cells can comprise access contact flaws which may become fatal with age, a testing method is provided wherein the cells (TGF1) are read by comparing a reference cell (TGF) current Iref with the sum of the current I of the tested cell and a bias current I'bias which is weaker than current Ibias which is used in modes other than the testing mode (i.e. in normal memory reading mode).