公开(公告)号：EP3295331A1

公开(公告)日：2018-03-21

申请号：EP15892049

申请日：2015-12-03

申请人： CAMBOU BERTRAND F

发明人： CAMBOU BERTRAND F

IPC分类号： G06F17/30

CPC分类号： G06F12/1408 ,  G06F3/0622 ,  G06F3/0653 ,  G06F3/0683 ,  G06F21/00 ,  G06F21/79 ,  G06F2212/1016 ,  G11C11/4076 ,  G11C11/4078 ,  G11C15/043 ,  H04L9/0894 ,  H04L9/3226 ,  Y02B60/1225 ,  Y02D10/13

摘要： A memory circuit using dynamic random access memory (DRAM) arrays. The DRAM arrays can be configured as CAMs or RAMs on the same die, with the control circuitry for performing comparisons located outside of the DRAM arrays. In addition, DRAM arrays can be configured for secure authentication where, after the first authentication performed with a non-volatile secure element, subsequent authentications can be performed by the DRAM array.

公开(公告)号：EP3304561A1

公开(公告)日：2018-04-11

申请号：EP15894493.4

申请日：2015-09-29

申请人： Cambou, Bertrand, F.

发明人： Cambou, Bertrand, F.

IPC分类号： G11C15/00

CPC分类号： G06F12/1408 ,  G06F12/1466 ,  G06F2212/1052 ,  G06F2212/402 ,  G11C7/24 ,  G11C11/005 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0059 ,  G11C13/0097 ,  G11C15/046 ,  G11C2013/008 ,  H04L9/14 ,  H04L9/30

摘要： A memory circuit using resistive random access memory (ReRAM) arrays in a secure element. The ReRAM arrays can be configured as content addressable memories (CAMs) or random access memories (RAMs) on the same die, with the control circuitry for performing comparisons of reference patterns and input patterns located outside of the ReRAM arrays. By having ReRAM arrays configured as CAMs and RAMs on the same die, certain reference patterns can be stored in CAMs and others in RAMs depending on security needs. For additional security, a heater can be used to erase reference patterns in the ReRAM arrays when desired.

公开(公告)号：EP3284066B1

公开(公告)日：2020-02-26

申请号：EP15889414.7

申请日：2015-07-16

申请人： Cambou, Bertrand, F.

发明人： Cambou, Bertrand, F.

IPC分类号： G06F21/40 ,  G06F21/45 ,  G06F21/31 ,  G11C15/04

公开(公告)号：EP3284093A1

公开(公告)日：2018-02-21

申请号：EP15889412.1

申请日：2015-06-24

申请人： Cambou, Bertrand, F.

发明人： Cambou, Bertrand, F.

IPC分类号： G11C15/04

CPC分类号： G11C15/046 ,  G06F21/31 ,  G06F21/316 ,  G06F21/40 ,  G06F21/45 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/20 ,  G11C17/14 ,  G11C17/18 ,  H04L63/08 ,  H04L2463/082

摘要： A memory circuit with blocking states. In one embodiment, the memory circuit includes a two non-volatile transistors connected in series. The input state of the memory cell and the stored state of the memory cell are configured to be a plurality of states including a zero state, a one state, a no care state, and an input blocking state. When the input state of the memory cell is the blocking state, the memory cell is configured to be in a blocking mode unless the stored state of the memory cell is the no care state. When the stored state of the memory cell is the blocking state, the memory cell is configured to be in the blocking mode unless the input state of the memory cell is the no care state.

公开(公告)号：EP3304561B1

公开(公告)日：2020-08-26

申请号：EP15894493.4

申请日：2015-09-29

申请人： Cambou, Bertrand, F.

发明人： Cambou, Bertrand, F.

IPC分类号： G11C15/04 ,  G11C11/00 ,  G11C13/00 ,  G06F12/14 ,  H04L9/14 ,  H04L9/30 ,  G11C7/24

公开(公告)号：EP3284066A1

公开(公告)日：2018-02-21

申请号：EP15889414.7

申请日：2015-07-16

申请人： Cambou, Bertrand, F.

发明人： Cambou, Bertrand, F.

IPC分类号： G07F7/10

CPC分类号： G11C15/046 ,  G06F21/31 ,  G06F21/316 ,  G06F21/40 ,  G06F21/45 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/20 ,  G11C17/14 ,  G11C17/18 ,  H04L63/08 ,  H04L2463/082

摘要： A memory circuit with blocking states. In one embodiment, the memory circuit includes a two non-volatile transistors connected in series. The input state of the memory cell and the stored state of the memory cell are configured to be a plurality of states including a zero state, a one state, a no care state, and an input blocking state. When the input state of the memory cell is the blocking state, the memory cell is configured to be in a blocking mode unless the stored state of the memory cell is the no care state. When the stored state of the memory cell is the blocking state, the memory cell is configured to be in the blocking mode unless the input state of the memory cell is the no care state.