公开(公告)号：EP0676081A1

公开(公告)日：1995-10-11

申请号：EP94903480.0

申请日：1993-12-06

申请人： LIPOVSKY, G., Jack

发明人： LIPOVSKY, G., Jack

IPC分类号： G06F7 ,  G06F12 ,  G06F17 ,  G11C7 ,  G11C11 ,  G11C15

CPC分类号： G06F17/30982 ,  G06F7/02 ,  G06F12/0866 ,  G06F2207/025 ,  G11C7/1006 ,  G11C11/406 ,  G11C15/04 ,  G11C15/043 ,  Y10S707/99936

摘要： The invention is a dynamic storage device (Figs. 3-10) requiring periodic refresh, and including logical operation circuitry (e.g., 21 and 24 of Fig.4) within the refresh circuitry (19 of Fig. 4). The individual storage positions of the storage device are periodically read by a refresh amplifier (RE of Fig. 4), and then a logical operation is performed on the refresh data before the data is applied to the write amplifier (WR of Fig. 4). This operation allows implementation of associative data base searching by cyclically executing data compare and other logical operations within the refresh circuitry. Storage systems for use with such devices (e.g., Fig. 12) are also disclosed.

公开(公告)号：EP0662663A2

公开(公告)日：1995-07-12

申请号：EP95100064.5

申请日：1995-01-03

申请人： Oki Electric Industry Co., Ltd.

发明人： Tanaka, Yasuhiro, c/o Oki Electr.Industry Co., Ltd ,  Tanabe, Tetsuya, c/o Oki Electr.Industry Co., Ltd. ,  Tanoi, Satoru, c/o Oki Electric Industry Co., Ltd.

IPC分类号： G06F12/08 ,  G11C7/00

CPC分类号： G11C7/106 ,  G06F12/0893 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/4096 ,  G11C15/04 ,  G11C15/043 ,  G11C2207/2245

摘要： A semiconductor memory device has memory cells for storing data, sense amplifiers for amplifying the stored data, and cache cells in which the amplified data can be placed for quick recall. The cache cells can continue to hold data during memory-cell refresh cycles, permitting the cached data to be accessed quickly afterward. The cache cells may be coupled to column data lines that can be disconnected from the sense amplifiers, enabling memory cells to be refreshed while cache access is in progress. Write buffers may be provided so that when cache data are replaced, the old cache data can be copied back to the memory cells while the new cache data are being accessed.

摘要翻译： 半导体存储器件具有用于存储数据的存储单元，用于放大所存储的数据的读出放大器，以及可放置放大数据以用于快速调用的高速缓存单元。 高速缓存单元可以在存储单元刷新周期期间继续保持数据，从而允许快速访问缓存的数据。 高速缓存单元可以耦合到可以从读出放大器断开的列数据线，使得能够刷新存储器单元，同时缓存访问正在进行。 可以提供写入缓冲器，使得当缓存数据被替换时，旧的缓存数据可以被复制回存储器单元，同时正在访问新的高速缓存数据。

公开(公告)号：EP0187822B1

公开(公告)日：1991-01-09

申请号：EP85903588.3

申请日：1985-06-28

申请人： AT&T Corp.

发明人： GREENBERGER, Alan, Joel

IPC分类号： G06F15/40

CPC分类号： G06F17/30979 ,  G06F17/30982 ,  G11C15/04 ,  G11C15/043

摘要： A semiconductor memory circuit is arranged with an ordinary crosspoint row-column array (100) of dynamic capacitor memory storage cells. Word serial content addressing is enable by adding a separate combinational logic device (101-105), only one such device for each entire column bit line, thereby reducing the number of elements normally required to achieved such addressing.

公开(公告)号：EP3295331A1

公开(公告)日：2018-03-21

申请号：EP15892049

申请日：2015-12-03

申请人： CAMBOU BERTRAND F

发明人： CAMBOU BERTRAND F

IPC分类号： G06F17/30

CPC分类号： G06F12/1408 ,  G06F3/0622 ,  G06F3/0653 ,  G06F3/0683 ,  G06F21/00 ,  G06F21/79 ,  G06F2212/1016 ,  G11C11/4076 ,  G11C11/4078 ,  G11C15/043 ,  H04L9/0894 ,  H04L9/3226 ,  Y02B60/1225 ,  Y02D10/13

摘要： A memory circuit using dynamic random access memory (DRAM) arrays. The DRAM arrays can be configured as CAMs or RAMs on the same die, with the control circuitry for performing comparisons located outside of the DRAM arrays. In addition, DRAM arrays can be configured for secure authentication where, after the first authentication performed with a non-volatile secure element, subsequent authentications can be performed by the DRAM array.

公开(公告)号：EP3025346A4

公开(公告)日：2017-03-29

申请号：EP14829677

申请日：2014-07-10

申请人： MICRON TECHNOLOGY INC

发明人： MANNING TROY A

IPC分类号： G11C15/04 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4096

CPC分类号： G11C7/065 ,  G11C7/06 ,  G11C7/062 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1048 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4096 ,  G11C15/043

摘要： The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.

公开(公告)号：EP1357558B1

公开(公告)日：2006-07-12

申请号：EP03009170.6

申请日：2003-04-22

申请人： Broadcom Corporation

发明人： Afghahi, Morteza Cyrus

IPC分类号： G11C15/04

CPC分类号： G11C15/04 ,  G11C15/043

公开(公告)号：EP1548747A1

公开(公告)日：2005-06-29

申请号：EP04030740.7

申请日：2004-12-23

申请人： Hitachi, Ltd. ,  Elpida Memory, Inc.

发明人： Hanzawa, Satoru ,  Sakata, Takeshi ,  Kajigaya, Kazuhiko

IPC分类号： G11C15/04

CPC分类号： G11C15/04 ,  G11C15/043

摘要： The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (comparison information or search key) are the common block code such that any bit must be the logical value '1'; Match-lines are hierarchically structured and memory cells are arranged at the intersecting points of a plurality of sub-match lines and a plurality of search lines; Further the sub-match lines are connected to main-match lines through the sub-match detectors, respectively and main-match detectors are arranged on the main-match lines.

摘要翻译： 的范围内指定的IP地址被存储有效减少条目必要从而TCAM的存储容量提高的数量。 本发明的代表性装置是在于：所述存储信息（条目）及输入信息（比较信息或搜索关键字）是常见的块码的搜索没有任何位必须为逻辑值“1”; 匹配线被层次结构化，并存储在电池子匹配条线的多个和的搜索线的多个交叉点布置; 此外，该子匹配线通过子匹配检测器分别连接到主匹配线，和主匹配检测器上的主匹配线地布置。

公开(公告)号：EP0187822A1

公开(公告)日：1986-07-23

申请号：EP85903588.0

申请日：1985-06-28

申请人： AT&T Corp.

发明人： GREENBERGER, Alan, Joel

IPC分类号： G11C15 ,  G06F17

CPC分类号： G06F17/30979 ,  G06F17/30982 ,  G11C15/04 ,  G11C15/043

摘要： Un circuit de mémoire à semi-conducteurs est disposé avec un réseau ordinaire de rangées et de colonnes à croisement (100) de cellules de stockage de mémoire à condensateur dynamique. L'adressage du contenu sériel des mots est validé par l'addition d'un dispositif logique combinatoire séparé (101-105), un seul dispositif similaire pour chaque ligne entière de bit de colonne, ce qui réduit le nombre d'éléments normalement requis pour effectuer un tel adressage.

摘要翻译： 半导体存储器电路设置有动态电容器存储器单元的行和交叉列（100）的普通阵列。 的字的串行内容寻址通过加入单独的组合逻辑装置（101-105），用于柱位的每个整条生产线，这减少了通常所需要的部件数量一个类似的装置的验证 执行这样的寻址。

公开(公告)号：EP3091448A4

公开(公告)日：2017-12-06

申请号：EP14874258

申请日：2014-12-18

申请人： INOUE KATSUMI

发明人： INOUE KATSUMI

IPC分类号： G06F17/30 ,  G11C7/10 ,  G11C15/04

CPC分类号： G06F17/30982 ,  G06F17/30 ,  G10L15/28 ,  G11C7/1006 ,  G11C15/00 ,  G11C15/04 ,  G11C15/043

摘要： CPUs are not effective for search processing for information on a memory. Content-addressable memories (CAMs) are effective for information searches, but it is difficult to build a large-capacity memory usable for big data using the CAMs. A large-capacity memory may be turned into an active memory having an information search capability comparable to that of a content-addressable memory (CAM) by incorporating an extremely small, single-bit-based parallel logical operation unit into a common memory. With this memory, a super fast in-memory database capable of fully parallel searches may be realized.

公开(公告)号：EP3127120A4

公开(公告)日：2017-11-15

申请号：EP15774178

申请日：2015-03-26

申请人： MICRON TECHNOLOGY INC

发明人： MANNING TROY A

IPC分类号： G11C7/10 ,  G11C7/06

CPC分类号： G11C15/043 ,  G11C7/1006 ,  G11C11/4091

摘要： Apparatuses and methods related to comparing data patterns in memory. An example method can include comparing a number of data patterns stored in a memory array to a target data pattern. The method can include determining whether a data pattern of the number of data patterns matches the target data pattern without transferring data from the memory array via an input/output (I/O) line.