利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

5 条记录 (耗时 0.01 秒)

    BUS DRIVER WITH DATA DEPENDENT DRIVE STRENGTH CONTROL LOGIC
    2.
    发明公开
    BUS DRIVER WITH DATA DEPENDENT DRIVE STRENGTH CONTROL LOGIC 审中-公开
    随着数据相关逻辑来驱动音量控制总线驱动器

    公开(公告)号：EP1163729A4

    公开(公告)日：2004-11-17

    申请号：EP00915866

    申请日：2000-02-25

    申请人： QLOGIC CORP

    发明人： CHAN TING-LI

    IPC分类号： G06F3/00 ,  G06F13/40 ,  H04B1/38 ,  H04B10/10 ,  H04B15/00 ,  H04L5/16 ,  H04L25/02 ,  H04L25/49 ,  H04M19/00

    CPC分类号： H04L25/028

    摘要： A transceiver circuit for transmitting a data signal over a communications bus (10) at a predefined bit rate includes a transmitter (4). The data signal is a digital signal having first and second logic levels. The transmitter (4) receives and modifies the data signal and feeds the modified data signal to the communications bus (10). The transmitter (4) includes a drive circuit (7) and an output circuit (6). The drive circuit (7) receives the data signal and a clock signal and generates control signals which depend on the logic level of the data signal. The control signals are sequentially generated when the data signal has consecutive bits of the same logic level. The output circuit (6) receives the control signals and the data signal and generates an output signal which corresponds to the data signal, but which has a varying drive strength determined by the control signals.

    CIRCUIT AND METHOD FOR RAPID CHECKING OF ERROR CORRECTION CODES USING CYCLIC REDUNDANCY CHECK
    3.
    发明公开
    CIRCUIT AND METHOD FOR RAPID CHECKING OF ERROR CORRECTION CODES USING CYCLIC REDUNDANCY CHECK 有权
    电路及方法快速检测FEHLERKORREKTURKODEN使用循环冗余校验

    公开(公告)号：EP1090462A4

    公开(公告)日：2002-01-02

    申请号：EP99925959

    申请日：1999-05-27

    申请人： QLOGIC CORP

    发明人： SZE HUNG Y

    IPC分类号： G11B20/18 ,  H03M13/00 ,  H03M13/15 ,  H03M13/29

    CPC分类号： G11B20/18 ,  H03M13/00 ,  H03M13/15 ,  H03M13/29

    摘要： A circuit and method uses CRC to check errors detected and corrected by an ECC unit (120) when reading data from a disk (116) in a disk drive (110). A CRC unit (118) monitors both the sector bytes read from the disk platter (114) and the error corrections made by the ECC unit (120) to the data and CRC bytes. The CRC unit (118) uses this information to determine whether the ECC-corrected data bytes stored in a buffer unit (122) were properly corrected. The CRC unit (118) reads data bytes and CRC bytes from the disk (116) simultaneously with the ECC unit (120). The CRC unit (118) begins generating a residue to detect errors in the data at approximately the same time the ECC unit (120) begins generating a residue to detect errors in the sector. The CRC unit (118) does not wait for the ECC unit (120) to finish and transfer the ECC error corrections into a buffer. The CRC error check is completed before any data is transferred to the host computer (112). In particular, the CRC unit (118) approves the data before the disk drive controller (126) sends the data to the host (112).

    METHOD AND CIRCUIT FOR RECEIVING DUAL EDGE CLOCKED DATA
    5.
    发明公开
    METHOD AND CIRCUIT FOR RECEIVING DUAL EDGE CLOCKED DATA 有权
    FOR TWO方法和电路TO END GETAKTEN数据接收

    公开(公告)号：EP1163569A4

    公开(公告)日：2002-05-15

    申请号：EP00910194

    申请日：2000-02-16

    申请人： QLOGIC CORP

    发明人： NGUYEN KHA

    IPC分类号： G06F13/36 ,  G06F5/06 ,  G06F13/38 ,  H04L7/00 ,  G06F1/12

    CPC分类号： G06F5/06

    摘要： A circuit (34) receives data asynchronously from a bus (48) on which the data is transferred on both rising and falling edges of a control signal (H-STROBE), and provides the data to an output (FIFO_DIN) synchronously with a local clock (SYSCLK). The circuit (34), which may be used in an Ultra DMA controller or other type of device (2) that receives data according to a dual clocked transfer scheme, advantageously, allows the dual edge clocked data to be received using the same controller clock frequency that would be used if the data were transferred only on a single edge. The circuit (34) includes a strobe generator (22) that generates strobes in response to the edges (502, 504, 506) of the control signal. The data from the bus (48) is provided to two temporary storage units (24, 26), one which stores the data transferred on rising edges and one which stores the data transferred on falling edges. The data is provided synchronously to the output of the circuit by using the strobes generated by the strobe generator (22) to select between the two temporary storage units (24, 26).