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公开(公告)号：EP4258543A3
公开(公告)日：2024-01-17
申请号：EP23187969.3
申请日：2019-11-29
申请人： Socionext Inc.
摘要： Quadrature oscillator circuitry, comprising: a first differential oscillator circuit having differential output nodes and configured to generate a first pair of differential oscillator signals at those output nodes, respectively; a second differential oscillator circuit having differential output nodes and configured to generate a second pair of differential oscillator signals at those output nodes, respectively; and a cross-coupling circuit connected to cross-couple the first and second differential oscillator circuits. The cross-coupling circuit may comprise a pair of cross-coupled transistors.
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公开(公告)号：EP4170911A1
公开(公告)日：2023-04-26
申请号：EP21203829.3
申请日：2021-10-20
申请人： Socionext Inc.
发明人： DARZY, Saul
IPC分类号： H03M1/78
摘要： Differential circuitry comprising first and second current paths each comprising a succession of first and further load nodes, each successive further load node connected to its preceding load node via a divider impedance; and first switching circuitry connected to the further load node or nodes of the first current path, and second switching circuitry connected to the further load node or nodes of the second current path, the first and second switching circuitry configured to control a magnitude of controllable current signals passing through the load nodes of the first current path and the second current path, respectively, wherein: the first load nodes of the first and second current paths comprise a first pair of load nodes, and the or each successive further load node of the first current path and its corresponding successive further load node of the second current path comprise a successive further pair of load nodes; the first pair of load nodes are connected to a first common node via respective first load impedances and the or each successive further pair of load nodes are connected to a successive further common node via respective further load impedances; the or each successive further common node is connected to its preceding common node; and the or at least one of the successive further common nodes is connected to its preceding common node via a resistor.
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公开(公告)号：EP3840220A1
公开(公告)日：2021-06-23
申请号：EP19219073.4
申请日：2019-12-20
申请人： Socionext Inc.
IPC分类号： H03D7/14
摘要： Differential mixer circuitry comprising: first and second input-voltage nodes and first and second input-current nodes; a passive network of impedances connected between the first and second input-voltage nodes and the first and second input-current nodes, and configured to convert first and second input-voltage signals received at the first and second input-voltage nodes, respectively, into first and second input-current signals provided at the first and second input-current nodes, respectively, the first and second input-voltage signals defining a differential input-voltage signal having an input frequency, and the first and second input-current signals defining a differential input-current signal; and a mixing stage configured to mix the differential input-current signal with at least one mixing signal having a corresponding mixing frequency and output a differential output signal having an output frequency dependent on the input frequency and each mixing frequency.
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公开(公告)号：EP3796558A1
公开(公告)日：2021-03-24
申请号：EP20200655.7
申请日：2017-09-15
申请人： Socionext Inc.
IPC分类号： H03K5/135 , H04L7/033 , H03K19/0185
摘要： The present disclosure relates to phase alignment, in particular to phase alignment circuitry (and parts thereof) for example for use in a multiplexer or other circuitry in which data is transmitted from one stage to another. Consideration is given to phase detection and phase rotation. Such circuitry may be implemented as integrated circuitry, for example on an IC chip.
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公开(公告)号：EP3672077A1
公开(公告)日：2020-06-24
申请号：EP18214275.2
申请日：2018-12-19
申请人： Socionext Inc.
发明人： RATTAN, Suhas
摘要： Comparator circuitry for use in a comparator to capture differences between magnitudes of a pair of comparator input signals in a series of capture operations defined by a reset signal, the circuitry comprising: latch circuitry (800), comprising a pair of latch input transistors (802, 804) which form corresponding parts of first and second current paths of the latch circuitry respectively, which current paths extend in parallel between high and low voltage sources, a pair of latch output nodes (314, 316) at corresponding positions along the first and second current paths of the latch circuitry respectively, and timing circuitry (326, 328, 806); and gain-stage circuitry (700), comprising a pair of cross-coupled gain-stage output transistors (710, 712) connected along respective first and second current paths of the gain-stage circuitry which extend in parallel between high and low voltage sources, and a pair of diode-connected gain-stage output transistors (714, 716) connected in parallel with the pair of cross-coupled gain-stage output transistors, respectively.
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公开(公告)号：EP3564856A1
公开(公告)日：2019-11-06
申请号：EP18170218.4
申请日：2018-04-30
申请人： Socionext Inc.
摘要： A method of evaluating image data representative of a display icon relative to reference data representative of a reference icon to determine whether the display icon matches the reference icon, the reference icon comprising at least first and second image regions which are distinct in image contrast from one another, the image data defining pixel values corresponding to pixels of the display icon, the method comprising: for each of a plurality of areas of the display icon, categorising that area as corresponding to one or none of the image regions based on a comparison between the pixel value or values for that area and at least a plurality of pixel-value ranges defined in relation to the reference icon, the pixel-value ranges corresponding to respective said image regions and defined so as to ensure sufficient image contrast between areas categorised as corresponding to different said image regions; generating categorisation information representative of the image data indicating how the plurality of areas have been categorised; and determining whether the display icon matches the reference icon based on a comparison of the categorisation information and the reference data.
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公开(公告)号：EP1562382B1
公开(公告)日：2019-09-04
申请号：EP05001465.3
申请日：2005-01-25
申请人： Socionext Inc.
发明人： OKADA, Masahiro , TANIKAWA, Yuji
IPC分类号： G11B27/034 , H04N5/765 , H04N21/236 , H04N21/434 , H04N21/4402 , H04N19/40
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公开(公告)号：EP3514965A1
公开(公告)日：2019-07-24
申请号：EP18152585.8
申请日：2018-01-19
申请人： Socionext Inc.
IPC分类号： H03M1/46
摘要： The present invention relates to analogue-to-digital converter (ADC) circuitry. In particular, the present invention relates to ADC circuitry configured to use successive approximation to arrive at a multi-bit digital value representative of an analogue input value.
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公开(公告)号：EP3477686A1
公开(公告)日：2019-05-01
申请号：EP16907234.5
申请日：2016-06-28
申请人： Socionext Inc.
发明人： YOSHITANI, Masanori
IPC分类号： H01L21/336 , H01L29/78
摘要： A semiconductor device includes: element isolation regions (14); a projecting semiconductor region (11); a plurality of first gate electrodes (12A) each formed on both side surfaces and a top surface of a portion of the projecting semiconductor region, the plurality of first gate electrodes being formed between a pair of opposed end portions of the element isolation regions; at least one second gate electrode (12B) formed between the first gate electrodes, in the same layer as a layer where the plurality of first gate electrodes are formed, and applied with a voltage for turning off a transistor; and source regions and drain regions formed in the projecting semiconductor region at both sides of the first gate electrodes and the second gate electrode. Between transistors each including the first gate electrode, a transistor including the second gate electrode applied with the voltage for turning off the transistors is disposed, thereby making it possible to reduce the heat generation in the transistors without reducing the saturation current of the transistors.
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