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公开(公告)号：EP4258543A3
公开(公告)日：2024-01-17
申请号：EP23187969.3
申请日：2019-11-29
申请人： Socionext Inc.
摘要： Quadrature oscillator circuitry, comprising: a first differential oscillator circuit having differential output nodes and configured to generate a first pair of differential oscillator signals at those output nodes, respectively; a second differential oscillator circuit having differential output nodes and configured to generate a second pair of differential oscillator signals at those output nodes, respectively; and a cross-coupling circuit connected to cross-couple the first and second differential oscillator circuits. The cross-coupling circuit may comprise a pair of cross-coupled transistors.
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公开(公告)号：EP4106204A1
公开(公告)日：2022-12-21
申请号：EP21180429.9
申请日：2021-06-18
申请人： Socionext Inc.
摘要： Phase Locked Loop, PLL, circuitry comprising a phase detector configured to generate a first pulse signal comprising at least one first pulse, a property of each first pulse being indicative of a phase difference between a reference signal and a feedback signal; a pulse repeater circuit configured, based on the first pulse signal, to generate a second pulse signal comprising, for each first pulse, a second pulse generated by repeating the corresponding first pulse; and an oscillator configured to generate the feedback signal and control a frequency of the feedback signal based on the second pulse signal.
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公开(公告)号：EP3514653A1
公开(公告)日：2019-07-24
申请号：EP18152588.2
申请日：2018-01-19
申请人： Socionext Inc.
摘要： Signal-generation circuitry comprising: a differential amplifier comprising first and second input transistors connected along first and second corresponding current paths, control terminals of the first and second input transistors serving as corresponding first and second input terminals of the differential amplifier, the differential amplifier having an output terminal at which an amplified signal is output dependent on first and second input signals received at the first and second input terminals, respectively; bandgap voltage reference circuitry also comprising said first current path having said first input transistor, the bandgap voltage reference circuitry further comprising a third current path having a third input transistor, wherein the control terminals of the first and third input transistors are connected together to form a reference terminal at which a bandgap voltage reference signal is generated as said first input signal; and a regulation stage connected to receive the amplified signal output from the differential amplifier and configured to generate a voltage-regulated signal based thereon, and connected to the second input terminal of the differential amplifier so that the second input signal is a feedback signal dependent on the voltage-regulated signal.
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公开(公告)号：EP3945681A1
公开(公告)日：2022-02-02
申请号：EP20188774.2
申请日：2020-07-30
申请人： Socionext Inc.
摘要： A leakage-current compensation circuit, comprising: a first node for connection of a first component thereto, whereby a first leakage current flows through the first component and through the first node with a given polarity with respect to the first node, the magnitude of the first leakage current dependent on a first potential difference across the first component; a second component connected to a second node and configured such that a second leakage current flows through the second component and through the second node, the magnitude of the second leakage current dependent on a second potential difference across the second component; a current mirror connected to the first node and the second node and configured to cause a compensation current to flow through the first node with opposite polarity to the first leakage current with respect to the first node, the magnitude of the compensation current dependent on the magnitude of the second leakage current due to current mirroring; a differential amplifier configured, based on a difference between the first potential difference and the second potential difference, to control a feedback component connected in series with the second component along a current path carrying the second leakage current to cause the second potential difference to track the first potential difference; and an AC coupling connected to superimpose an AC-component of the first potential difference on the second potential difference.
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公开(公告)号：EP3829068A1
公开(公告)日：2021-06-02
申请号：EP19212615.9
申请日：2019-11-29
申请人： Socionext Inc.
摘要： Transformer circuitry comprising: a transformer having a primary coil and a secondary coil, the primary coil having first and second primary terminals and the secondary coil having first and second secondary terminals, and a secondary coil driver configured to drive a secondary voltage signal V2 across the secondary terminals which has a target relationship with a primary voltage signal V1 driven across the primary terminals by a primary coil driver so that an inductance value measured between the primary terminals is governed by the target relationship.
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公开(公告)号：EP3829056A1
公开(公告)日：2021-06-02
申请号：EP19212645.6
申请日：2019-11-29
申请人： Socionext Inc.
摘要： Quadrature oscillator circuitry (800), comprising: a first differential oscillator circuit having differential output nodes (12, 22) and configured to generate a first pair of differential oscillator signals (I+, I-) at those output nodes, respectively; a second differential oscillator circuit having differential output nodes (12, 22) and configured to generate a second pair of differential oscillator signals (Q+, Q-) at those output nodes, respectively; and a cross-coupling circuit (802, 804) connected to cross-couple the first and second differential oscillator circuits. The cross-coupling circuit may comprise a pair of cross-coupled transistors.
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公开(公告)号：EP4258543A2
公开(公告)日：2023-10-11
申请号：EP23187969.3
申请日：2019-11-29
申请人： Socionext Inc.
IPC分类号： H03B27/00
摘要： Quadrature oscillator circuitry, comprising: a first differential oscillator circuit having differential output nodes and configured to generate a first pair of differential oscillator signals at those output nodes, respectively; a second differential oscillator circuit having differential output nodes and configured to generate a second pair of differential oscillator signals at those output nodes, respectively; and a cross-coupling circuit connected to cross-couple the first and second differential oscillator circuits. The cross-coupling circuit may comprise a pair of cross-coupled transistors.
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公开(公告)号：EP3839991A1
公开(公告)日：2021-06-23
申请号：EP19219092.4
申请日：2019-12-20
申请人： Socionext Inc.
摘要： An inductor arrangement, comprising: a first pair of driven inductors configured to be driven to generate magnetic fields which are substantially in antiphase, and arranged relative to one another so that their magnetic fields substantially cancel one another at a first null line between those inductors; and a second pair of driven inductors configured to produce magnetic fields which are substantially in antiphase, and arranged relative to one another so that their magnetic fields substantially cancel one another at a second null line between those inductors, wherein the pairs of driven inductors are arranged relative to one another so that the first and second null lines intersect one another, with the first pair of driven inductors located substantially on the second null line and the second pair of inductors located substantially on the first null line
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公开(公告)号：EP3829066A1
公开(公告)日：2021-06-02
申请号：EP19212625.8
申请日：2019-11-29
申请人： Socionext Inc.
IPC分类号： H03K19/0185
摘要： Clock distribution circuitry (100) for distributing a clock signal across integrated circuitry, the clock distribution circuitry comprising: a clock transmitter (20) comprising first and second transmission nodes (22, 24) and configured to generate first and second currents, defining a transmitter differential clock signal, at the first and second transmission nodes, respectively; a clock receiver (30) comprising first and second reception nodes (32, 34) and first and second current paths (36, 38) which extend between the first and second reception nodes and a voltage supply node (VDD) via first and second clock output nodes (VOUT-, VOUT+), respectively, wherein first and second load impedances (RL1, RL2) are connected to form respective parts of the first and second current paths between the first and second clock output nodes and the voltage supply node, and first and second impedance-matching transistors (M3, M4) are connected to form respective parts of the first and second current paths between the first and second reception nodes and the first and second clock output nodes, respectively; and first and second transmission lines (TL1, TL2) connected between the first and second transmission nodes and the first and second reception nodes, respectively, to cause the first and second currents to flow along the first and second current paths and induce output voltage signals at the first and second clock output nodes, respectively, which define a receiver differential clock signal. The first and second impedance-matching transistors are configured so that the input impedances of the clock receiver at the first and second reception nodes substantially match the characteristic impedances of the first and second transmission lines, respectively.
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公开(公告)号：EP3514961A1
公开(公告)日：2019-07-24
申请号：EP18152586.6
申请日：2018-01-19
申请人： Socionext Inc.
IPC分类号： H03L7/089
摘要： Charge pump circuitry comprising: a reference current path, an auxiliary current path and an output current path connected in parallel between high and low voltage sources; and a differential amplifier configured to generate an amplifier output signal based upon a difference between first and second input signals, wherein: the reference current path is configured to cause a reference current to flow along that path; the reference, auxiliary and output current paths comprise respective first current-mirror transistors connected in a first current-mirror arrangement so that an auxiliary current flowing along the auxiliary current path and a first output current flowing along a first part of the output current path are dependent on the reference current flowing along the reference current path due to current mirroring; the auxiliary and output current paths comprise respective second-current-mirror transistors connected in a second current-mirror arrangement so that a second output current flowing along a second part of the output current path is dependent on the auxiliary current flowing along the auxiliary current path due to current mirroring; the output current path comprises an output node for connection to an external load to allow current to flow between the charge pump circuitry and the external load dependent on the first and second output currents; the auxiliary current path comprises a control transistor connected in series with the first-current-mirror transistor of that path; and the differential amplifier is connected to receive its first and second input signals from nodes in the auxiliary and output current paths, respectively, at which nodes the signals generated are indicative of the drain or collector voltages of the first-current mirror transistors in those paths, and configured to control the control transistor with its amplifier output signal so as to control the drain or collector voltage of the first-current mirror transistor in the auxiliary path.
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