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    SIC-ON-SI-BASED SEMICONDUCTOR MODULE WITH SHORT CIRCUIT FAILURE MODE
    2.
    发明公开
    SIC-ON-SI-BASED SEMICONDUCTOR MODULE WITH SHORT CIRCUIT FAILURE MODE 审中-公开
    基于SIC-ON-SI的半导体模块具有短路故障模式

    公开(公告)号：EP3306663A1

    公开(公告)日：2018-04-11

    申请号：EP16192299.2

    申请日：2016-10-05

    申请人： ABB Schweiz AG

    发明人： LIU, Chunlei ,  RAHIMO, Munaf ,  STEIMER, Peter

    IPC分类号： H01L23/62 ,  H01L23/051 ,  H01L25/07

    CPC分类号： H01L23/34 ,  H01L23/051 ,  H01L23/492 ,  H01L23/5252 ,  H01L23/62 ,  H01L24/72 ,  H01L25/072

    摘要： A semiconductor module (10) comprises a semiconductor chip (12) comprising a Si base layer (14) and a SiC epitaxy layer (16) on the Si base layer (14), the SiC epitaxy layer (16) comprising a semiconductor element (17); an electrical conducting top layer (Mo) (24) for providing an electrical contact of the semiconductor module (10) on a side of the SiC epitaxy layer (16); an electrical conducting bottom layer (Mo) (22) for providing an electrical contact of the semiconductor module (10) on a side of the Si base layer (14); and a failure mode layer (26, 26a, 26b) in contact with a top and/or bottom surface (18, 20) of the semiconductor chip (12) and arranged between the top layer (24) and the bottom layer (22), the failure mode layer (26, 26a, 26b) comprising a metal material (Al, Cu, Ag, Au) (27) adapted for forming a conducting path with the Si base layer (14), for example for forming a eutectic alloy with the Si base layer (14), to short-circuit the semiconductor module (10). The failure mode layer (26, 26b) at the bottom surface (20) of the semiconductor chip (12) may be coated to a core (30) of the bottom layer (22).

    摘要翻译： 半导体模块（10）包括在Si基底层（14）上包括Si基底层（14）和SiC外延层（16）的半导体芯片（12），SiC外延层（16）包括半导体元件 17）; 用于在所述SiC外延层（16）的一侧上提供所述半导体模块（10）的电接触的导电顶层（Mo）（24）; 用于在所述Si基底层（14）的一侧上提供所述半导体模块（10）的电接触的导电底层（Mo）（22）; 和与半导体芯片（12）的顶部和/或底部表面（18,20）接触并且布置在顶层（24）和底层（22）之间的故障模式层（26,26a，26b） ，所述故障模式层（26,26a，26b）包括适于与所述Si基底层（14）形成导电路径的金属材料（Al，Cu，Ag，Au）（27），例如用于形成共晶合金 与Si基极层（14）一起短路半导体模块（10）。 半导体芯片（12）的底表面（20）处的故障模式层（26,26b）可以被涂覆到底层（22）的芯（30）。

    POWER SEMICONDUCTOR DEVICE WITH ACTIVE SHORT CIRCUIT FAILURE MODE
    3.
    发明公开
    POWER SEMICONDUCTOR DEVICE WITH ACTIVE SHORT CIRCUIT FAILURE MODE 审中-公开

    公开(公告)号：EP3577687A1

    公开(公告)日：2019-12-11

    申请号：EP18704183.5

    申请日：2018-01-31

    申请人： ABB Schweiz AG

    发明人： LIU, Chunlei ,  DUGAL, Franc ,  RAHIMO, Munaf ,  STEIMER, Peter Karl

    IPC分类号： H01L23/62 ,  H01L25/07 ,  H01L29/16 ,  H01L23/051 ,  H01L23/535

    摘要： A power semiconductor device includes a Si chip providing a Si switch and a wide bandgap material chip providing a wide bandgap material switch, wherein the Si switch and the wide bandgap material switch are electrically connected in parallel. A method for controlling a power semiconductor device includes: during a normal operation mode, controlling at least the wide bandgap material switch for switching a current through the power semiconductor device by applying corresponding gate signals to at least the wide bandgap material switch; sensing a failure in the power semiconductor device; and, in the case of a sensed failure, controlling the Si switch by applying a gate signal, such that a current is generated in the Si chip heating the Si chip to a temperature forming a permanent conducting path through the Si chip.

    POWER SEMICONDUCTOR MODULE WITH SHORT CIRCUIT FAILURE MODE
    4.
    发明公开
    POWER SEMICONDUCTOR MODULE WITH SHORT CIRCUIT FAILURE MODE 审中-公开

    公开(公告)号：EP3566246A1

    公开(公告)日：2019-11-13

    申请号：EP18704192.6

    申请日：2018-02-01

    申请人： ABB Schweiz AG

    发明人： LIU, Chunlei ,  SCHUDERER, Jürgen ,  BREM, Franziska ,  RAHIMO, Munaf ,  STEIMER, Peter Karl ,  DUGAL, Franc

    IPC分类号： H01L23/051 ,  H01L23/535 ,  H01L23/62 ,  H01L25/07 ,  H01L29/16 ,  H01L23/00

    摘要： A power semiconductor device includes a base plate; a Si chip including a Si substrate, the Si chip attached to the base plate; a first metal preform pressed with a first press pin against the Si chip; a wide bandgap material chip comprising a wide bandgap substrate and a semiconductor switch provided in the wide bandgap substrate, the wide bandgap material chip attached to the base plate; and a second metal preform pressed with a second press pin against the wide bandgap material chip; the Si chip and the wide bandgap material chip are connected in parallel via the base plate and via the first press pin and the second press pin; the first metal preform is adapted for forming a conducting path through the Si chip, when heated by an overcurrent; and the second metal preform is adapted for forming an temporary conducting path through the wide bandgap material chip or an open circuit, when heated by an overcurrent.