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    POWER MODULE WITH LOW STRAY INDUCTANCE
    3.
    发明公开
    POWER MODULE WITH LOW STRAY INDUCTANCE 审中-公开
    低电感电源模块

    公开(公告)号：EP3246945A1

    公开(公告)日：2017-11-22

    申请号：EP16170452.3

    申请日：2016-05-19

    申请人： ABB Schweiz AG ,  AUDI AG

    发明人： COTTET, Didier ,  TRAUB, Felix

    IPC分类号： H01L25/07 ,  H01L23/538 ,  H02M7/00

    CPC分类号： H01L23/142 ,  H01L23/24 ,  H01L23/5386 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/0603 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2924/1304 ,  H01L2924/19107 ,  H01L2924/30107 ,  H02M7/003

    摘要： A power module (10) providing a half bridge (32) comprises at least one substrate (12) and an inner metallization area (16), two intermediate metallization areas (18) and two outer metallization areas (20), each of which extends in a longitudinal direction (L) of the at least one substrate (12); wherein the two intermediate metallization areas (18) are arranged besides the inner metallization area (16) with respect to a cross direction (C) of the at least one substrate (12) and each outer metallization area (20) is arranged beside one of the two intermediate metallization areas (18) with respect to the cross direction (C); wherein the power module (10) comprises two inner sets (22) of semiconductor switches (24), each inner set (22) of semiconductor switches (24) bonded to an intermediate metallization area (18) and electrically connected to the inner metallization area (16), such that the inner sets (22) of semiconductor switches (24) form a first arm (34) of the half bridge (32); wherein the power module (10) comprises two outer sets (28) of semiconductor switches (24), each outer set (28) of semiconductor switches (24) bonded to an outer metallization area (20) and electrically connected to an intermediate metallization area (18), such that the outer sets (28) of semiconductor switches (24) form a second arm (36) of the half bridge (32).

    摘要翻译： 提供半桥（32）的功率模块（10）包括至少一个衬底（12）和内部金属化区域（16），两个中间金属化区域（18）和两个外部金属化区域（20），每个中间金属化区域 在所述至少一个衬底（12）的纵向方向（L）上; 其中所述两个中间金属化区域（18）相对于所述至少一个衬底（12）的横向（C）布置在所述内部金属化区域（16）之外，并且每个外部金属化区域（20）布置在所述至少一个 两个中间金属化区域（18）相对于横向（C）; 其中功率模块（10）包括两个半导体开关（24）的内部组（22），半导体开关（24）的每个内部组（22）结合到中间金属化区域（18）并且电连接到内部金属化区域 （16），使得半导体开关（24）的内部组（22）形成半桥（32）的第一臂（34）; 其特征在于，所述功率模块（10）包括两个半导体开关（24）的外部组（28），每个外部组（28）半导体开关（24）接合到外部金属化区域（20）并且电连接到中间金属化区域 （18），使得半导体开关（24）的外组（28）形成半桥（32）的第二臂（36）。

    POWER MODULE WITH LOW STRAY INDUCTANCE
    4.
    发明授权
    POWER MODULE WITH LOW STRAY INDUCTANCE 有权

    公开(公告)号：EP3246945B1

    公开(公告)日：2018-10-03

    申请号：EP16170452.3

    申请日：2016-05-19

    申请人： ABB Schweiz AG ,  AUDI AG

    发明人： COTTET, Didier ,  TRAUB, Felix

    IPC分类号： H01L25/18 ,  H01L23/24 ,  H01L25/07 ,  H02M7/00 ,  H01L23/538

    CPC分类号： H01L23/142 ,  H01L23/24 ,  H01L23/5386 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/0603 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2924/1304 ,  H01L2924/19107 ,  H01L2924/30107 ,  H02M7/003

    摘要： A power module (10) providing a half bridge (32) comprises at least one substrate (12) and an inner metallization area (16), two intermediate metallization areas (18) and two outer metallization areas (20), each of which extends in a longitudinal direction (L) of the at least one substrate (12); wherein the two intermediate metallization areas (18) are arranged besides the inner metallization area (16) with respect to a cross direction (C) of the at least one substrate (12) and each outer metallization area (20) is arranged beside one of the two intermediate metallization areas (18) with respect to the cross direction (C); wherein the power module (10) comprises two inner sets (22) of semiconductor switches (24), each inner set (22) of semiconductor switches (24) bonded to an intermediate metallization area (18) and electrically connected to the inner metallization area (16), such that the inner sets (22) of semiconductor switches (24) form a first arm (34) of the half bridge (32); wherein the power module (10) comprises two outer sets (28) of semiconductor switches (24), each outer set (28) of semiconductor switches (24) bonded to an outer metallization area (20) and electrically connected to an intermediate metallization area (18), such that the outer sets (28) of semiconductor switches (24) form a second arm (36) of the half bridge (32).

    HALF-BRIDGE MODULE WITH COAXIAL ARRANGEMENT OF THE DC TERMINALS
    7.
    发明公开
    HALF-BRIDGE MODULE WITH COAXIAL ARRANGEMENT OF THE DC TERMINALS 审中-公开

    公开(公告)号：EP3613077A1

    公开(公告)日：2020-02-26

    申请号：EP18720620.6

    申请日：2018-04-30

    申请人： ABB Schweiz AG ,  Audi AG

    发明人： MOHN, Fabian ,  TRAUB, Felix ,  SCHUDERER, Jürgen

    IPC分类号： H01L25/07 ,  H01L23/498 ,  H01L23/538

    摘要： A half-bridge module includes a substrate with a base metallization layer divided into a first DC conducting area, a second DC conducting area and an AC conducting area; at least one first power semiconductor switch chip bonded to the first DC conducting area and electrically interconnected with the AC conducting area; at least one second power semiconductor switch chip bonded to the AC conducting area and electrically interconnected with the second DC conducting area; and a coaxial terminal arrangement including at least one inner DC terminal, the at least first outer DC terminal and the at least one second outer DC terminal protrude from the module and are arranged in a row, such that the at least one inner DC terminal is coaxially arranged between the at least one first outer DC terminal and the at least one second outer DC terminal; wherein the at least one inner DC terminal is electrically connected to the second DC conducting area; the at least one first outer DC terminal and the at least one second outer DC terminal are electrically connected to the first DC conducting area; and the at least one first outer DC terminal and the at least one second outer DC terminal are electrically interconnected with an electrically conducting bridging element which is adapted for distributing at least a half of the load current between the at least one first outer DC terminal and the at least one second outer DC terminal.