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    Programmable high-speed voltage-mode differential driver
    2.
    发明公开
    Programmable high-speed voltage-mode differential driver 审中-公开
    可编程高速电压模式差分驱动器

    公开(公告)号：EP2814216A3

    公开(公告)日：2015-02-11

    申请号：EP14169882.9

    申请日：2014-05-26

    申请人： Altera Corporation

    发明人： Wang, Bonnie I. ,  Ding, Weiqi ,  Hoang, Tim Tri ,  Hernandez, Richard ,  Lin, Haidang

    IPC分类号： H04L25/02 ,  H03K19/0185

    CPC分类号： H03F3/45071 ,  H03K19/018514 ,  H03K19/018585 ,  H04L25/0272

    摘要： A voltage-mode differential driver (105) is disclosed. The differential driver (105) includes two driver arms (110-P, 110-N), each driver arm (110-P, 110-N) including a variable-impedance driver (116) for driving a single-ended output signal. Each variable-impedance driver (116) comprises multiple driver slices, where each driver slice includes a pre-driver circuit and a driver circuit. Advantageously, it has been determined that the disclosed voltage-mode driver design requires less power than conventional current-mode drivers. In one implementation, the disclosed voltage-mode driver design provides the capability of independently programming the delay of the two single-ended outputs so as to compensate for differential skew. Other embodiments and features are also disclosed.

    摘要翻译： 公开了一种电压模式差分驱动器（105）。 差分驱动器（105）包括两个驱动臂（110-P，110-N），每个驱动臂（110-P，110-N）包括用于驱动单端输出信号的可变阻抗驱动器（116）。 每个可变阻抗驱动器（116）包括多个驱动器片，其中每个驱动器片包括预驱动器电路和驱动器电路。 有利地，已经确定所公开的电压模式驱动器设计需要比常规电流模式驱动器更少的功率。 在一个实现中，所公开的电压模式驱动器设计提供独立编程两个单端输出的延迟以补偿差分偏斜的能力。 其他实施例和特征也被公开。

    Programmable high-speed I/O interface
    3.
    发明公开
    Programmable high-speed I/O interface 有权
    Programmierbare Hochgeschwindigkeits-E / A-Schnittstelle

    公开(公告)号：EP1852976A1

    公开(公告)日：2007-11-07

    申请号：EP07016191.4

    申请日：2002-08-26

    申请人： Altera Corporation

    发明人： Wang, Bonnie I. ,  Sung, Chiakang ,  Huang, Joseph ,  Nguyen, Khai ,  Pan, Philip

    IPC分类号： H03K19/177 ,  H03K19/0185

    CPC分类号： H03K19/17744 ,  H03K19/17792

    摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

    摘要翻译： 提供高速或低速灵活输入和输出的方法和设备。 提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。 选择其中一个输入和输出电路，并取消选择其他电路。 高速输入和输出电路相当简单，在一个示例中，仅具有用于控制线路输入的清除信号，并且能够与集成电路的核心内的低速电路接口。 低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线输入，并且能够支持JTAG边界测试。 这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

    Programmable High-Speed I/O Interface
    4.
    发明公开
    Programmable High-Speed I/O Interface 有权
    程序员schnelle Eingangs- / Ausgangsschnittstelle

    公开(公告)号：EP1294099A3

    公开(公告)日：2004-03-17

    申请号：EP02255977.7

    申请日：2002-08-28

    申请人： Altera Corporation

    发明人： Wang, Bonnie I. ,  Sung, Chiakang ,  Huang, Joseph ,  Nguyen, Khai ,  Pan, Philip

    IPC分类号： H03K19/177 ,  H03K19/0185

    CPC分类号： H03K19/17744 ,  H03K19/0175 ,  H03K19/017509 ,  H03K19/017581 ,  H03K19/1774 ,  H03K19/17788

    摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

    摘要翻译： 提供高速或低速灵活输入和输出的方法和设备。 提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。 选择其中一个输入和输出电路，并取消选择其他电路。 高速输入和输出电路相当简单，在一个示例中，仅具有用于控制线路输入的清除信号，并且能够与集成电路的核心内的低速电路接口。 低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线输入，并且能够支持JTAG边界测试。 这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

    Programmable High-Speed I/O Interface
    5.
    发明公开
    Programmable High-Speed I/O Interface 有权
    可编程快速输入/输出接口

    公开(公告)号：EP1294099A2

    公开(公告)日：2003-03-19

    申请号：EP02255977.7

    申请日：2002-08-28

    申请人： Altera Corporation

    发明人： Wang, Bonnie I. ,  Sung, Chiakang ,  Huang, Joseph ,  Nguyen, Khai ,  Pan, Philip

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17744 ,  H03K19/0175 ,  H03K19/017509 ,  H03K19/017581 ,  H03K19/1774 ,  H03K19/17788

    摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

    LVDS interface incorporating phase-locked loop circuitry for use in programmable logic device
    6.
    发明公开
    LVDS interface incorporating phase-locked loop circuitry for use in programmable logic device 有权
    LVDS接口电子邮件程序员登录Vorrichtung

    公开(公告)号：EP1018805A2

    公开(公告)日：2000-07-12

    申请号：EP99310576.6

    申请日：1999-12-24

    申请人： Altera Corporation

    发明人： Sung, Chiakang ,  Wang, Bonnie I. ,  Cliff, Richard G.

    IPC分类号： H03K5/15 ,  H03K5/135 ,  G06F1/10

    CPC分类号： H03L7/18 ,  H03L7/07 ,  H03L7/0891

    摘要： An LVDS interface for a programmable logic device uses phase-locked loop ("PLL") circuits to provide data clocks for data input and output. The PLL clocks are highly accurate and each includes a multiply-by-W counter so that a multiplied and an unmultiplied clock are available. The multiplied clock is used to clock data into or out of a shift register chain serially. The unmultiplied clock is used to load or read the registers in the shift register chain in parallel. Providing both the multiplied and unmultiplied clocks from a single PLL assures that the clocks are in proper phase relationship so that the serial inputting or outputting, and the parallel loading or unloading, are properly synchronized.

    摘要翻译： 用于可编程逻辑器件的LVDS接口使用锁相环（“PLL”）电路为数据输入和输出提供数据时钟。 PLL时钟是高精度的，每个都包括一个乘以W的计数器，以便可以使用倍增和非乘法时钟。 倍增时钟用于将数据串行时移到或移出移位寄存器链。 非乘法时钟用于并行加载或读取移位寄存器链中的寄存器。 同时提供来自单个PLL的倍增和非乘法时钟，确保时钟处于正确的相位关系，以便串行输入或输出以及并行加载或卸载被正确同步。

    Programmable high-speed voltage-mode differential driver
    7.
    发明公开
    Programmable high-speed voltage-mode differential driver 审中-公开
    Hochgeschwindigkeitstreiber程序员

    公开(公告)号：EP2814216A2

    公开(公告)日：2014-12-17

    申请号：EP14169882.9

    申请日：2014-05-26

    申请人： Altera Corporation

    发明人： Wang, Bonnie I. ,  Ding, Weiqi ,  Hoang, Tim Tri ,  Hernandez, Richard ,  Lin, Haidang

    IPC分类号： H04L25/02

    CPC分类号： H03F3/45071 ,  H03K19/018514 ,  H03K19/018585 ,  H04L25/0272

    摘要： A voltage-mode differential driver (105) is disclosed. The differential driver (105) includes two driver arms (110-P, 110-N), each driver arm (110-P, 110-N) including a variable-impedance driver (116) for driving a single-ended output signal. Each variable-impedance driver (116) comprises multiple driver slices, where each driver slice includes a pre-driver circuit and a driver circuit. Advantageously, it has been determined that the disclosed voltage-mode driver design requires less power than conventional current-mode drivers. In one implementation, the disclosed voltage-mode driver design provides the capability of independently programming the delay of the two single-ended outputs so as to compensate for differential skew. Other embodiments and features are also disclosed.

    摘要翻译： 公开了电压模式差分驱动器（105）。 差分驱动器（105）包括两个驱动器臂（110-P，110-N），每个驱动臂（110-P，110-N）包括用于驱动单端输出信号的可变阻抗驱动器（116）。 每个可变阻抗驱动器（116）包括多个驱动器片，其中每个驱动器片包括预驱动器电路和驱动器电路。 有利地，已经确定所公开的电压模式驱动器设计比常规电流模式驱动器需要更少的功率。 在一个实现中，所公开的电压模式驱动器设计提供了独立编程两个单端输出的延迟的能力，以补偿差分偏移。 还公开了其它实施例和特征。

    LVDS interface incorporating phase-locked loop circuitry for use in programmable logic device
    10.
    发明公开
    LVDS interface incorporating phase-locked loop circuitry for use in programmable logic device 有权
    用相LVDS接口锁相环用于可编程逻辑器件

    公开(公告)号：EP1018805A3

    公开(公告)日：2000-07-19

    申请号：EP99310576.6

    申请日：1999-12-24

    申请人： Altera Corporation

    发明人： Sung, Chiakang ,  Wang, Bonnie I. ,  Cliff, Richard G.

    IPC分类号： H03K5/15 ,  H03K5/135 ,  G06F1/10

    CPC分类号： H03L7/18 ,  H03L7/07 ,  H03L7/0891

    摘要： An LVDS interface for a programmable logic device uses phase-locked loop ("PLL") circuits to provide data clocks for data input and output. The PLL clocks are highly accurate and each includes a multiply-by-W counter so that a multiplied and an unmultiplied clock are available. The multiplied clock is used to clock data into or out of a shift register chain serially. The unmultiplied clock is used to load or read the registers in the shift register chain in parallel. Providing both the multiplied and unmultiplied clocks from a single PLL assures that the clocks are in proper phase relationship so that the serial inputting or outputting, and the parallel loading or unloading, are properly synchronized.