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公开(公告)号：EP3168739A1
公开(公告)日：2017-05-17
申请号：EP16198393.7
申请日：2016-11-11
申请人： ARM Limited
摘要： A display controller 12 comprises a first display processing core 20 comprising a first input stage 21 operable to read at least one input surface, a first processing stage operable to process one or more input surfaces to generate an output surface, and a first output stage 26 operable to provide an output surface for display to a first display 6, and a second display processing core 40 comprising a second input stage 41 operable to read at least one input surface, a second processing stage operable to process one or more input surfaces to generate an output surface, and a second output stage 46 operable to provide an output surface for display to a second display 8. The display controller 12 also comprises an internal data path 30 for passing pixel data of an output surface from the second display core 40 to the first display core 20.
摘要翻译： 显示控制器12包括第一显示处理核心20和第一输出级26，第一显示处理核心20包括可操作以读取至少一个输入表面的第一输入级21，可操作以处理一个或多个输入表面以产生输出表面的第一处理级， 可操作以提供用于显示到第一显示器6的输出表面，以及第二显示处理核心40，其包括可操作以读取至少一个输入表面的第二输入级41，可操作以处理一个或一个以上输入表面以产生 输出表面和第二输出级46，第二输出级46可操作以提供用于显示到第二显示器8的输出表面。显示控制器12还包括内部数据路径30，用于将来自第二显示核心40的输出表面的像素数据传递到 第一显示核心20。
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公开(公告)号：EP3095037B1
公开(公告)日：2018-08-08
申请号：EP15700149.6
申请日：2015-01-06
申请人： ARM Limited
IPC分类号： G06F13/364 , G06F13/40 , G06F13/42 , G06F12/0831
CPC分类号： G06F13/4068 , G06F12/0831 , G06F13/364 , G06F13/4022 , G06F13/4221 , G06F2212/1016 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A data processing system having a master device and a plurality of slave devices uses interconnect circuitry to couple the master device with the plurality of slave devices to enable transactions to be performed by the slave devices upon request from the master device. The master device issues a multi-transaction request identifying multiple transactions to be performed, the multi-transaction request providing a base transaction identifier, a quantity indication indicating a number of transactions to be performed, and address information. Request distribution circuitry within the interconnect circuitry analyses the address information and the quantity indication in order to determine, for each of the multiple transactions, the slave device that is required to perform that transaction. Transaction requests are then issued from the request distribution circuitry to each determined slave device to identify which transactions need to be performed by each slave device. Each determined slave device provides a response to the master device to identify completion of each transaction performed by that determined slave device. Each determined slave device provides its responses independently of the responses from any other determined slave device, and each response includes a transaction identifier determined from the base transaction identifier and transaction specific information. This enables the master device to identify completion of each transaction identified within the multi-transaction request. In an alternative arrangement, the same multi-transaction request approach can be used by a master device to initiate cache maintenance operations within a plurality of cache storage devices. This approach can give rise to significant improvements in efficiency and power consumption within the data processing system.
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公开(公告)号：EP3095037A1
公开(公告)日：2016-11-23
申请号：EP15700149.6
申请日：2015-01-06
申请人： ARM Limited
IPC分类号： G06F13/40
CPC分类号： G06F13/4068 , G06F12/0831 , G06F13/364 , G06F13/4022 , G06F13/4221 , G06F2212/1016 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A data processing system having a master device and a plurality of slave devices uses interconnect circuitry to couple the master device with the plurality of slave devices to enable transactions to be performed by the slave devices upon request from the master device. The master device issues a multi-transaction request identifying multiple transactions to be performed, the multi-transaction request providing a base transaction identifier, a quantity indication indicating a number of transactions to be performed, and address information. Request distribution circuitry within the interconnect circuitry analyses the address information and the quantity indication in order to determine, for each of the multiple transactions, the slave device that is required to perform that transaction. Transaction requests are then issued from the request distribution circuitry to each determined slave device to identify which transactions need to be performed by each slave device. Each determined slave device provides a response to the master device to identify completion of each transaction performed by that determined slave device. Each determined slave device provides its responses independently of the responses from any other determined slave device, and each response includes a transaction identifier determined from the base transaction identifier and transaction specific information. This enables the master device to identify completion of each transaction identified within the multi-transaction request. In an alternative arrangement, the same multi-transaction request approach can be used by a master device to initiate cache maintenance operations within a plurality of cache storage devices. This approach can give rise to significant improvements in efficiency and power consumption within the data processing system.
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