公开(公告)号：EP2488951B1

公开(公告)日：2015-01-07

申请号：EP10763398.4

申请日：2010-09-28

申请人： ARM Limited

发明人： RIOCREUX, Peter Andrew ,  MATHEWSON, Bruce James ,  LAYCOCK, Christopher William ,  GRISENTHWAITE, Richard, Roy

IPC分类号： G06F13/16

CPC分类号： G06F13/362 ,  G06F13/1621 ,  G06F13/1689 ,  G06F13/364

公开(公告)号：EP4288867A1

公开(公告)日：2023-12-13

申请号：EP22703696.9

申请日：2022-02-02

申请人： ARM Limited

发明人： GARCIA-TOBIN, Carlos ,  MATHEWSON, Bruce James ,  EVANS, Matthew Lucien ,  GRISENTHWAITE, Richard Roy

IPC分类号： G06F12/1009 ,  G06F12/1027

公开(公告)号：EP3788494A1

公开(公告)日：2021-03-10

申请号：EP19723174.9

申请日：2019-05-02

申请人： ARM Limited

发明人： MANNAVA, Phanindra Kumar ,  MATHEWSON, Bruce James ,  JALAL, Jamshed ,  RINGE, Tushar P

IPC分类号： G06F12/0831 ,  G06F12/0813 ,  G06F12/0817

公开(公告)号：EP3580657A1

公开(公告)日：2019-12-18

申请号：EP17825915.6

申请日：2017-12-20

申请人： ARM Limited

发明人： MANNAVA, Phanindra Kumar ,  MATHEWSON, Bruce James ,  BRUCE, Klas Magnus ,  LACOURBA, Geoffray Matthieu

IPC分类号： G06F9/52

公开(公告)号：EP2488954B1

公开(公告)日：2015-11-25

申请号：EP10775868.2

申请日：2010-10-12

申请人： ARM Limited

发明人： RIOCREUX, Peter Andrew ,  MATHEWSON, Bruce James ,  LAYCOCK, Christopher William ,  GRISENTHWAITE, Richard Roy

IPC分类号： G06F13/40 ,  G06F13/16

CPC分类号： G06F13/362 ,  G06F13/1621 ,  G06F13/1689 ,  G06F13/364

公开(公告)号：EP2488954A1

公开(公告)日：2012-08-22

申请号：EP10775868.2

申请日：2010-10-12

申请人： ARM Limited

发明人： RIOCREUX, Peter Andrew ,  MATHEWSON, Bruce James ,  LAYCOCK, Christopher William ,  GRISENTHWAITE, Richard Roy

IPC分类号： G06F13/40 ,  G06F13/16

CPC分类号： G06F13/362 ,  G06F13/1621 ,  G06F13/1689 ,  G06F13/364

摘要： An initiator device for issuing transaction requests to a recipient device via an interconnect is disclosed. The initiator device comprises: at least one port for receiving requests from and issuing requests to said interconnect; a barrier generator for generating barrier transaction requests, the barrier transaction requests indicating to the interconnect that an ordering of at least some transaction requests within a stream of transaction requests passing through the interconnect should be maintained by not allowing reordering of at least some of the transaction requests that occur before the barrier transaction request in the stream of transaction requests with respect to the barrier transaction request; wherein in response to receipt of a synchronise request querying progress of at least a subset of transaction requests, the initiator device is responsive to action any pending transaction requests within the at least a subset of transaction request and to generate a barrier transaction request at the barrier generator and to issue the barrier transaction request to the interconnect via the at least one port, and in response to receiving a response to the barrier transaction request to issue an acknowledge signal as a response to the synchronise request.

公开(公告)号：EP3800555A1

公开(公告)日：2021-04-07

申请号：EP20190264.0

申请日：2020-08-10

申请人： ARM Limited

发明人： MANNAVA, Phanindra Kumar ,  MATHEWSON, Bruce James ,  JALAL, Jamshed

IPC分类号： G06F12/0811 ,  G06F12/126

摘要： Apparatus has plurality of requester elements and a cache hierarchy. A requester element issues a cache maintenance operation request specifying a memory address range to push a data block through at least one level of the cache hierarchy and to make that block visible to other requester elements. The given requester element detects when there is a need to issue a write request prior to the cache maintenance operation request in order to cause a write operation to be performed in respect of data within the specified memory address range, and issues a combined write and cache maintenance operation request instead of a write request and a subsequent cache maintenance operation request. A recipient completer element that receives the combined request initiates processing of the cache maintenance operation without waiting for the write operation to complete. This reduces latency in handling of cache maintenance operations, and reduces bandwidth utilisation.

公开(公告)号：EP3095037B1

公开(公告)日：2018-08-08

申请号：EP15700149.6

申请日：2015-01-06

申请人： ARM Limited

发明人： MATHEWSON, Bruce James ,  CROXFORD, Daren ,  PARKER, Jason

IPC分类号： G06F13/364 ,  G06F13/40 ,  G06F13/42 ,  G06F12/0831

CPC分类号： G06F13/4068 ,  G06F12/0831 ,  G06F13/364 ,  G06F13/4022 ,  G06F13/4221 ,  G06F2212/1016 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： A data processing system having a master device and a plurality of slave devices uses interconnect circuitry to couple the master device with the plurality of slave devices to enable transactions to be performed by the slave devices upon request from the master device. The master device issues a multi-transaction request identifying multiple transactions to be performed, the multi-transaction request providing a base transaction identifier, a quantity indication indicating a number of transactions to be performed, and address information. Request distribution circuitry within the interconnect circuitry analyses the address information and the quantity indication in order to determine, for each of the multiple transactions, the slave device that is required to perform that transaction. Transaction requests are then issued from the request distribution circuitry to each determined slave device to identify which transactions need to be performed by each slave device. Each determined slave device provides a response to the master device to identify completion of each transaction performed by that determined slave device. Each determined slave device provides its responses independently of the responses from any other determined slave device, and each response includes a transaction identifier determined from the base transaction identifier and transaction specific information. This enables the master device to identify completion of each transaction identified within the multi-transaction request. In an alternative arrangement, the same multi-transaction request approach can be used by a master device to initiate cache maintenance operations within a plurality of cache storage devices. This approach can give rise to significant improvements in efficiency and power consumption within the data processing system.

公开(公告)号：EP3265917A1

公开(公告)日：2018-01-10

申请号：EP16701195.6

申请日：2016-01-12

申请人： ARM Limited

发明人： PARKER, Jason ,  MATHEWSON, Bruce James ,  EVANS, Matthew

IPC分类号： G06F12/08 ,  G06F12/10

CPC分类号： G06F12/0833 ,  G06F12/0831 ,  G06F12/10 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/655 ,  Y02D10/13

摘要： An apparatus (2) comprises processing circuitry (4) for performing data processing in response to instructions. The processing circuitry (4) supports a cache maintenance instruction (50) specifying a virtual page address (52) identifying a virtual page of a virtual address space. In response to the cache maintenance instruction, the processing circuitry (4) triggers at least one cache (18, 20, 22) to perform a cache maintenance operation on one or more cache lines for which a physical address of the data stored by the cache line is within a physical page that corresponds to the virtual page identified by the virtual page address provided by the cache maintenance instruction.

公开(公告)号：EP3095037A1

公开(公告)日：2016-11-23

申请号：EP15700149.6

申请日：2015-01-06

申请人： ARM Limited

发明人： MATHEWSON, Bruce James ,  CROXFORD, Daren ,  PARKER, Jason

IPC分类号： G06F13/40

CPC分类号： G06F13/4068 ,  G06F12/0831 ,  G06F13/364 ,  G06F13/4022 ,  G06F13/4221 ,  G06F2212/1016 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： A data processing system having a master device and a plurality of slave devices uses interconnect circuitry to couple the master device with the plurality of slave devices to enable transactions to be performed by the slave devices upon request from the master device. The master device issues a multi-transaction request identifying multiple transactions to be performed, the multi-transaction request providing a base transaction identifier, a quantity indication indicating a number of transactions to be performed, and address information. Request distribution circuitry within the interconnect circuitry analyses the address information and the quantity indication in order to determine, for each of the multiple transactions, the slave device that is required to perform that transaction. Transaction requests are then issued from the request distribution circuitry to each determined slave device to identify which transactions need to be performed by each slave device. Each determined slave device provides a response to the master device to identify completion of each transaction performed by that determined slave device. Each determined slave device provides its responses independently of the responses from any other determined slave device, and each response includes a transaction identifier determined from the base transaction identifier and transaction specific information. This enables the master device to identify completion of each transaction identified within the multi-transaction request. In an alternative arrangement, the same multi-transaction request approach can be used by a master device to initiate cache maintenance operations within a plurality of cache storage devices. This approach can give rise to significant improvements in efficiency and power consumption within the data processing system.