公开(公告)号：EP4444047A1

公开(公告)日：2024-10-09

申请号：EP24164724.7

申请日：2024-03-20

申请人： AT&S (Chongqing) Company Limited

发明人： WANG, JyunMin ,  FUNG, James ,  ZHOU, Brance ,  LI, Stella ,  WEI, Vivi ,  DUAN, Cain ,  XIE, Melody ,  ZHOU, Lucas

IPC分类号： H05K1/02 ,  H05K1/11 ,  H05K3/42 ,  H05K3/00

CPC分类号： H05K3/0047 ,  H05K3/0055 ,  H05K2203/079620130101 ,  H05K2201/207220130101 ,  H05K2203/118420130101 ,  H05K1/0298 ,  H05K2203/07220130101 ,  H05K2203/030720130101 ,  H05K2201/0956320130101 ,  H05K3/002 ,  H05K2201/0961820130101 ,  H05K2201/0950920130101 ,  H05K2201/0985420130101 ,  H05K3/421 ,  H05K1/115

摘要： The present application provides a component carrier and a method of manufacture the same, the component carrier, comprising: a stack with a plurality of electrically insulating layer structures and one or more electrically conductive layer structures ,
the one or more electrically conductive layer structures comprise two opposed conductive surfaces ;
a plurality of first vias , formed at a front side of the stack , the plurality of first vias is connected to one of the two opposed conductive surfaces through a respective first baseline etch surface ; and
a plurality of second vias , formed at a back side of the stack, the front side is opposed to the back side , wherein the plurality of second vias is connected to the other one of the two opposed conductive surfaces through a respective second baseline etch surface .
The total area defined by the first baseline etch surfaces is higher than the total area defined by the second baseline etch surfaces and the depth of at least one of the first baseline etch surfaces is lower than the depth of at least one of the second baseline etch surfaces.