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    Interconnection and input/output resources for programmable logic integrated circuit devices
    1.
    发明公开
    Interconnection and input/output resources for programmable logic integrated circuit devices 有权
    可编程逻辑集成电路器件的互连和输入/输出资源

    公开(公告)号：EP1705798A3

    公开(公告)日：2009-03-11

    申请号：EP06011288.5

    申请日：2000-03-02

    申请人： Altera Corporation

    发明人： Ngai, Tony ,  Pederson, Bruce ,  Shumarayev, Sergey ,  Schleicher, James ,  Huang, Wei-Jen ,  Hutton, Michael ,  Maruri, Victor ,  Patel, Rakesh ,  Kazarian, Peter, J. ,  Leaver, Andrew ,  Mendel, David, W. ,  Park, Jim

    IPC分类号： H03K19/177 ,  H03K19/173

    CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/1774 ,  H03K19/17744

    摘要： A programmable logic integrated circuit device (10) has a plurality of regions (20) of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources (200a, 210a, 230a) may have what may be termed normal signal speed, while a smaller minor portion (200b, 210b, 230b) may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

    摘要翻译： 可编程逻辑集成电路器件（10）具有可编程逻辑的多个区域（20），这些可编程逻辑的区域（20）以这些区域的多个相交的行和列排列在器件上。 在器件上提供互连资源（例如互连导体，信号缓冲器/驱动器，可编程连接器等），用于在区域之间和/或之间形成可编程互连。 这些互连资源中的至少一些资源以结构上相似的两种形式提供（例如，具有类似的并且基本上平行的路由），但是具有显着不同的信号传播速度特性。 例如，这种双形式互连资源（200a，210a，230a）的主要或更大部分可具有可称为正常信号速度的部分，而较小的较小部分（200b，210b，230b）可具有明显更快的信号速度 。 次级（例如，时钟和清除）信号分配也可以被增强，并且因此可以是设备上相邻或附近逻辑模块之间的输入/输出电路和级联连接。

    Interconnection resources for programmable logic integrated circuit devices
    2.
    发明公开
    Interconnection resources for programmable logic integrated circuit devices 审中-公开
    可编程逻辑集成电路器件的互连资源

    公开(公告)号：EP1465345A3

    公开(公告)日：2006-04-12

    申请号：EP04012039.6

    申请日：2000-03-02

    申请人： ALTERA CORPORATION

    发明人： Schleicher, James ,  Shumarayev, Sergey ,  Pederson, Bruce ,  Ngai, Tony ,  Huang, Wei-Jen ,  Maruri, Victor ,  Patel, Rakesh

    IPC分类号： H03K19/177 ,  H03K19/173

    CPC分类号： H03K19/17736 ,  H03K19/17728 ,  H03K19/17792

    摘要： A programmable logic device has many regions of programmable logic, together with relatively general-purpose programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

    摘要翻译： 可编程逻辑器件具有许多可编程逻辑区域以及相对通用的可编程互连资源，这些资源可用于在几乎任何逻辑区域之间进行互连。 另外，各种类型的更多本地互连资源与每个逻辑区域相关联，以便于在相邻或附近逻辑区域之间进行互连，而不需要为这些互连使用通用互连资源。 本地互连资源支持通过相对直接且因此高速互连的逻辑区域的灵活集群，优选地在典型的逻辑区域的二维阵列中的水平和垂直方向上。 由本地互连资源提供的逻辑区域群集选项优选地在逻辑区域阵列内无边界或基本无边界。

    Interconnection and input/output resources for programmable logic integrated circuit devices
    7.
    发明公开
    Interconnection and input/output resources for programmable logic integrated circuit devices 有权
    Verbindungsressourcenfürprogrammierbare，logisch integrierte Schaltungen

    公开(公告)号：EP1705797A2

    公开(公告)日：2006-09-27

    申请号：EP06011287.7

    申请日：2000-03-02

    申请人： Altera Corporation

    发明人： Ngai, Tony ,  Pederson, Bruce ,  Shumarayev, Sergey ,  Schleicher, James ,  Huang, Wei-Jen ,  Hutton, Michael ,  Maruri, Victor ,  Patel, Rakesh ,  Kazarian, Peter, J. ,  Leaver, Andrew ,  Mendel, David, W. ,  Park, Jim

    IPC分类号： H03K19/177 ,  H03K19/173

    CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/1774 ,  H03K19/17744

    摘要： A programmable logic integrated circuit device (10) has a plurality of regions (20) of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources (200a, 210a, 230a) may have what may be termed normal signal speed, while a smaller minor portion (200b, 210b, 230b) may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

    摘要翻译： 可编程逻辑集成电路器件（10）具有多个可编程逻辑区域（20），该多个可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。 在设备上提供互连资源（例如，互连导体，信号缓冲器/驱动器，可编程连接器等），用于对区域之间和/或之间进行可编程互连。 这些互连资源中的至少一些以架构上相似的两种形式提供（例如，具有相似和基本上并行的路由），但具有显着不同的信号传播速度特性。 例如，这种双形式互连资源（200a，210a，230a）的主要或更大部分可以具有称为正常信号速度，而较小次要部分（200b，210b，230b）可具有明显更快的信号速度 。 辅助（例如，时钟和清除）信号分配也可以被增强，因此也可以是设备上的相邻或附近逻辑模块之间的输入/输出电路和级联连接。

    Logic element and method
    8.
    发明公开
    Logic element and method 审中-公开
    逻辑元件，并且所述方法

    公开(公告)号：EP1445864A3

    公开(公告)日：2005-12-14

    申请号：EP04250564.4

    申请日：2004-02-03

    申请人： ALTERA CORPORATION

    发明人： Lewis, David ,  Lee, Andy ,  Pederson, Bruce ,  Kaptanoglu, Sinan

    IPC分类号： H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/17728 ,  H03K19/1737

    摘要： A logic element (100) includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexer with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexer and a first level of multiplexer (110) with inputs connected to outputs of a second level of multiplexer (106) and at least one output (114). Controls (104,108,112) are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output (114) of the first level of multiplexer (110), and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs (118,120) of multiplexers (106,116) not at the first level of multiplexer.

    Interconnection resources for programmable logic integrated circuit devices
    9.
    发明公开
    Interconnection resources for programmable logic integrated circuit devices 审中-公开
    Verbindungsressourcenfürprogrammierbare，logisch integrierte Schaltungen

    公开(公告)号：EP1465345A2

    公开(公告)日：2004-10-06

    申请号：EP04012039.6

    申请日：2000-03-02

    申请人： Altera Corporation

    发明人： Schleicher, James ,  Shumarayev, Sergey ,  Pederson, Bruce ,  Ngai, Tony ,  Huang, Wei-Jen ,  Maruri, Victor ,  Patel, Rakesh

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736 ,  H03K19/17728 ,  H03K19/17792

    摘要： A programmable logic device has many regions of programmable logic, together with relatively general-purpose programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

    摘要翻译： 可编程逻辑器件具有许多可编程逻辑区域，以及相对通用的可编程互连资源，可用于在几乎任何逻辑区域之间进行互连。 此外，各种类型的更多本地互连资源与每个逻辑区域相关联，以便于在相邻或附近逻辑区域之间进行互连，而不需要为这些互连使用通用互连资源。 本地互连资源通过逻辑区域的典型二维阵列中的相对直接且因此高速互连，优选地在水平和垂直方向上支持逻辑区域的灵活聚类。 由本地互连资源提供的逻辑区域聚类选项优选地在逻辑区域阵列内是无边界的或基本上无边界的。

    Logic element and method
    10.
    发明公开
    Logic element and method 审中-公开
    Logisches Element und Dessen Verfahren

    公开(公告)号：EP1445864A2

    公开(公告)日：2004-08-11

    申请号：EP04250564.4

    申请日：2004-02-03

    申请人： Altera Corporation

    发明人： Lewis, David ,  Lee, Andy ,  Pederson, Bruce ,  Kaptanoglu, Sinan

    IPC分类号： H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/17728 ,  H03K19/1737

    摘要： A logic element (100) includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexer with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexer and a first level of multiplexer (110) with inputs connected to outputs of a second level of multiplexer (106) and at least one output (114). Controls (104,108,112) are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output (114) of the first level of multiplexer (110), and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs (118,120) of multiplexers (106,116) not at the first level of multiplexer.

    摘要翻译： 逻辑元件（100）包括存储器元件，多路复用器和控制器。 多路复用器被布置在包括最高级别的多路复用器的级别中，其中连接到存储器元件的输入端和连接到下一级到最高级别的多路复用器的输入端的输出端和第一级多路复用器（110），其输入端连接到 第二级复用器（106）和至少一个输出（114）。 控制器（104,108,112）连接到多路复用器。 在第一操作模式中，控制确定第一级多路复用器（110）的至少一个输出（114）处的第一模式输出，并且在第二操作模式中，控制确定选定的多个第二模式输出 多路复用器（106,116）的输出（118,120）不在多路复用器的第一级。