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    Interconnection and input/output resources for programmable logic integrated circuit devices
    1.
    发明公开
    Interconnection and input/output resources for programmable logic integrated circuit devices 有权
    可编程逻辑集成电路器件的互连和输入/输出资源

    公开(公告)号：EP1705798A3

    公开(公告)日：2009-03-11

    申请号：EP06011288.5

    申请日：2000-03-02

    申请人： Altera Corporation

    发明人： Ngai, Tony ,  Pederson, Bruce ,  Shumarayev, Sergey ,  Schleicher, James ,  Huang, Wei-Jen ,  Hutton, Michael ,  Maruri, Victor ,  Patel, Rakesh ,  Kazarian, Peter, J. ,  Leaver, Andrew ,  Mendel, David, W. ,  Park, Jim

    IPC分类号： H03K19/177 ,  H03K19/173

    CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/1774 ,  H03K19/17744

    摘要： A programmable logic integrated circuit device (10) has a plurality of regions (20) of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources (200a, 210a, 230a) may have what may be termed normal signal speed, while a smaller minor portion (200b, 210b, 230b) may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

    摘要翻译： 可编程逻辑集成电路器件（10）具有可编程逻辑的多个区域（20），这些可编程逻辑的区域（20）以这些区域的多个相交的行和列排列在器件上。 在器件上提供互连资源（例如互连导体，信号缓冲器/驱动器，可编程连接器等），用于在区域之间和/或之间形成可编程互连。 这些互连资源中的至少一些资源以结构上相似的两种形式提供（例如，具有类似的并且基本上平行的路由），但是具有显着不同的信号传播速度特性。 例如，这种双形式互连资源（200a，210a，230a）的主要或更大部分可具有可称为正常信号速度的部分，而较小的较小部分（200b，210b，230b）可具有明显更快的信号速度 。 次级（例如，时钟和清除）信号分配也可以被增强，并且因此可以是设备上相邻或附近逻辑模块之间的输入/输出电路和级联连接。

    STATE VISIBILITY AND MANIPULATION IN INTEGRATED CIRCUITS
    4.
    发明授权
    STATE VISIBILITY AND MANIPULATION IN INTEGRATED CIRCUITS 有权

    公开(公告)号：EP3159817B1

    公开(公告)日：2018-08-22

    申请号：EP16192391.7

    申请日：2016-10-05

    申请人： Altera Corporation

    发明人： Hutton, Michael ,  Atsatt, Sean

    IPC分类号： G06F17/50 ,  H03K19/177

    CPC分类号： G06F17/5027 ,  G06F17/5054 ,  G06F17/5068 ,  H03K19/177 ,  H03K19/17756 ,  H03K19/1776

    摘要： In a first mode, a control circuit may implement a circuit design with storage circuits in an integrated circuit by programming configuration memory bits via configuration resources. The storage circuits may be accessed for read and write operations during the execution of the circuit design implementation with the integrated circuit. In a second mode, the control circuit may perform read and write access operations at the storage circuits via configuration resources or via an interface circuit and interconnect resources that are allocated to the circuit design implementation. Typical applications for performing access operations at the storage circuits include fault injection and observation, statistical monitoring of the circuit design, initialization and the distribution of certain signals such as reset signals, event sampling, just to name a few.

    METHOD AND CIRCUIT FOR SCALABLE CROSS POINT SWITCHING USING 3-D DIE STACKING
    5.
    发明公开
    METHOD AND CIRCUIT FOR SCALABLE CROSS POINT SWITCHING USING 3-D DIE STACKING 审中-公开
    方法与电路可扩展的交叉点电路中使用3D芯片TAPE LUNG

    公开(公告)号：EP2947893A1

    公开(公告)日：2015-11-25

    申请号：EP15168439.6

    申请日：2015-05-20

    申请人： Altera Corporation

    发明人： Schulz, Jeffrey ,  Hutton, Michael

    IPC分类号： H04Q3/55

    CPC分类号： H03K19/1735 ,  G06F13/4022 ,  G06F15/17375 ,  G06F15/7867 ,  H03K19/1737 ,  H04Q3/552

    摘要： A cross-point switch having stacked switching dies on a component die is disclosed. The cross point switch allows scalability by adding switching dies. The switching dies include ingress switches that are coupled to multiplexers to a middle stage switches. The inputs and outputs of the ingress switches are connected to the switching interface region via through silicon vias (TSVs). The outputs of the ingress switches are also coupled by TSVs to multiplexers for routing to middle stage switches on a switching die above. If the switching die is stacked on another switching die, the outputs of the ingress switches are coupled by TSVs to the multiplexers for routing to the middle stage switches of the switching die below. By adding switching dies, the switch is configurable to increase the number of ports as well as the width of the ports.

    摘要翻译： 具有堆叠交叉点开关切换它是游离缺失盘组件上。 交叉点开关通过添加切换这允许可扩展性。 切换这包括入口交换机没有被耦合到多路转换器到中间级开关。 入口开关的输入和输出经由通过硅通孔（TSV），其连接到开关接口区域。 因此，入口开关的输出由TSV的耦合到多路转换器，用于路由到中间级开关上的开关的上方。 如果其被堆叠在另一个的切换开关，入口开关的输出通过的TSV耦合到多路转换器，用于路由到的切换下方的中间级开关。 通过添加切换此，所述开关是可配置的，以增加端口数量以及端口的宽度。

    METHOD AND CIRCUIT FOR SCALABLE CROSS POINT SWITCHING USING 3-D DIE STACKING
    6.
    发明授权
    METHOD AND CIRCUIT FOR SCALABLE CROSS POINT SWITCHING USING 3-D DIE STACKING 有权

    公开(公告)号：EP2947893B1

    公开(公告)日：2018-10-10

    申请号：EP15168439.6

    申请日：2015-05-20

    申请人： Altera Corporation

    发明人： Schulz, Jeffrey ,  Hutton, Michael

    IPC分类号： H04Q3/55

    CPC分类号： H03K19/1735 ,  G06F13/4022 ,  G06F15/17375 ,  G06F15/7867 ,  H03K19/1737 ,  H04Q3/552

    摘要： A cross-point switch having stacked switching dies on a component die is disclosed. The cross point switch allows scalability by adding switching dies. The switching dies include ingress switches that are coupled to multiplexers to a middle stage switches. The inputs and outputs of the ingress switches are connected to the switching interface region via through silicon vias (TSVs). The outputs of the ingress switches are also coupled by TSVs to multiplexers for routing to middle stage switches on a switching die above. If the switching die is stacked on another switching die, the outputs of the ingress switches are coupled by TSVs to the multiplexers for routing to the middle stage switches of the switching die below. By adding switching dies, the switch is configurable to increase the number of ports as well as the width of the ports.

    STATE VISIBILITY AND MANIPULATION IN INTEGRATED CIRCUITS
    7.
    发明公开
    STATE VISIBILITY AND MANIPULATION IN INTEGRATED CIRCUITS 审中-公开
    集成电路中的状态可见度和操作

    公开(公告)号：EP3159817A1

    公开(公告)日：2017-04-26

    申请号：EP16192391.7

    申请日：2016-10-05

    申请人： Altera Corporation

    发明人： Hutton, Michael ,  Atsatt, Sean

    IPC分类号： G06F17/50 ,  H03K19/177

    CPC分类号： G06F17/5027 ,  G06F17/5054 ,  G06F17/5068 ,  H03K19/177 ,  H03K19/17756 ,  H03K19/1776

    摘要： In a first mode, a control circuit may implement a circuit design with storage circuits in an integrated circuit by programming configuration memory bits via configuration resources. The storage circuits may be accessed for read and write operations during the execution of the circuit design implementation with the integrated circuit. In a second mode, the control circuit may perform read and write access operations at the storage circuits via configuration resources or via an interface circuit and interconnect resources that are allocated to the circuit design implementation. Typical applications for performing access operations at the storage circuits include fault injection and observation, statistical monitoring of the circuit design, initialization and the distribution of certain signals such as reset signals, event sampling, just to name a few.

    摘要翻译： 在第一模式中，控制电路可以通过经由配置资源编程配置存储器位来实现具有集成电路中的存储电路的电路设计。 存储电路可以在集成电路执行电路设计实现期间被访问用于读取和写入操作。 在第二模式中，控制电路可以经由配置资源或经由分配给电路设计实现的接口电路和互连资源在存储电路处执行读取和写入访问操作。 在存储电路上执行访问操作的典型应用包括故障注入和观察，电路设计的统计监控，初始化和某些信号（如复位信号，事件采样等）的分配。

    Interconnection and input/output resources for programmable logic integrated circuit devices
    10.
    发明公开
    Interconnection and input/output resources for programmable logic integrated circuit devices 有权
    Verbindungsressourcenfürprogrammierbare，logisch integrierte Schaltungen

    公开(公告)号：EP1705797A2

    公开(公告)日：2006-09-27

    申请号：EP06011287.7

    申请日：2000-03-02

    申请人： Altera Corporation

    发明人： Ngai, Tony ,  Pederson, Bruce ,  Shumarayev, Sergey ,  Schleicher, James ,  Huang, Wei-Jen ,  Hutton, Michael ,  Maruri, Victor ,  Patel, Rakesh ,  Kazarian, Peter, J. ,  Leaver, Andrew ,  Mendel, David, W. ,  Park, Jim

    IPC分类号： H03K19/177 ,  H03K19/173

    CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/1774 ,  H03K19/17744

    摘要： A programmable logic integrated circuit device (10) has a plurality of regions (20) of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources (200a, 210a, 230a) may have what may be termed normal signal speed, while a smaller minor portion (200b, 210b, 230b) may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

    摘要翻译： 可编程逻辑集成电路器件（10）具有多个可编程逻辑区域（20），该多个可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。 在设备上提供互连资源（例如，互连导体，信号缓冲器/驱动器，可编程连接器等），用于对区域之间和/或之间进行可编程互连。 这些互连资源中的至少一些以架构上相似的两种形式提供（例如，具有相似和基本上并行的路由），但具有显着不同的信号传播速度特性。 例如，这种双形式互连资源（200a，210a，230a）的主要或更大部分可以具有称为正常信号速度，而较小次要部分（200b，210b，230b）可具有明显更快的信号速度 。 辅助（例如，时钟和清除）信号分配也可以被增强，因此也可以是设备上的相邻或附近逻辑模块之间的输入/输出电路和级联连接。