公开(公告)号：EP3104530A1

公开(公告)日：2016-12-14

申请号：EP16172738.3

申请日：2016-06-02

申请人： Analog Devices, Inc.

发明人： NGUYEN, Khiem Quang

IPC分类号： H03M3/02 ,  H03M3/04

摘要： Power consumption of analog-to-digital converters (ADCs) is one important requirement for automotive and consumer devices. One flavor of an ADC is a dual quantizer architecture for oversampling delta-sigma modulators. The dual quantizer delta-sigma modulator has a first quantizer for digitizing the output of the loop filter and a second quantizer for digitizing the input of the quantizer. However, the quantization noise of the second quantizer is a highly correlated signal and significantly degrades the spectrum of the delta-sigma modulator. To address this issue, an improvement to the dual quantizer architecture is made to cancel the quantization noise of the second quantizer that is digitizing the input. Furthermore, the improvement allows the second quantizer to run at a much slower sampling rate than the first quantizer. Advantageously, the improvement provides reduction in power consumption and the overall area of modulator.

摘要翻译： 模数转换器（ADC）的功耗是汽车和消费类设备的一个重要要求。 ADC的一种风格是用于过采样delta-sigma调制器的双量化器架构。 双量化器Δ-Σ调制器具有用于数字化环路滤波器的输出的第一量化器和用于数字化量化器的输入的第二量化器。 然而，第二量化器的量化噪声是高度相关的信号，并且显着降低了Δ-Σ调制器的频谱。 为了解决这个问题，对双量化器架构进行了改进以消除正在对输入进行数字化的第二量化器的量化噪声。 此外，改进允许第二量化器以比第一量化器慢得多的采样速率运行。 有利地，该改进提供了功率消耗的降低和调制器的总面积。

公开(公告)号：EP3104530B1

公开(公告)日：2020-05-27

申请号：EP16172738.3

申请日：2016-06-02

申请人： Analog Devices, Inc.

发明人： NGUYEN, Khiem Quang

IPC分类号： H03M3/02 ,  H03M3/04

公开(公告)号：EP3190709A1

公开(公告)日：2017-07-12

申请号：EP17157464.3

申请日：2013-11-20

申请人： Analog Devices, Inc.

发明人： NGUYEN, Khiem Quang ,  ADAMS, Robert

IPC分类号： H03M1/06 ,  H03M1/74

CPC分类号： H03M1/66 ,  H03M1/0668 ,  H03M1/067 ,  H03M1/74 ,  H03M3/464

摘要： A multi-bit digital to analog converter comprising a plurality of unit cells, each providing an electrical signal to a common output at multiple levels in response to a respective control signal and a control system having multiple layers of branch circuits. Each branch circuit comprises a dynamic element matching circuit receiving a plurality of least significant bits of an input code to generate respective output signals to the control system and a plurality of branches, each receiving most significant bits of an input code to the respective layer and having an adder for the most significant bits of the layer's input signal and a respective output from the dynamic element matching circuit. An input signal to the digital to analog converter is input to a first layer as that layer's input code, input codes of the other layers are taken from output signals of preceding layers, and output signals of a last layer may be input to the unit cells as control signals.

摘要翻译： 一种多位数模转换器，包括多个单位单元，每个单位单元响应于相应的控制信号向多个级别的公共输出提供电信号，以及具有多层分支电路的控制系统。 每个分支电路包括动态元件匹配电路，该动态元件匹配电路接收输入码的多个最低有效位以产生到控制系统的相应输出信号和多个分支，每个分支接收输入码的最高有效位到相应层并且具有 用于层的输入信号的最高有效位的加法器和来自动态元件匹配电路的相应输出。 数模转换器的输入信号作为该层的输入代码被输入到第一层，其他层的输入代码从前一层的输出信号中获取，并且最后一层的输出信号可以被输入到单位单元 作为控制信号。