公开(公告)号：EP0621539A1

公开(公告)日：1994-10-26

申请号：EP94301988.5

申请日：1994-03-21

申请人： Compaq Computer Corporation

发明人： Thome, Gary W. ,  Collins, Michael J.

IPC分类号： G06F13/42 ,  G11C8/00 ,  G06F13/28

CPC分类号： G11C8/18 ,  G06F13/4243 ,  G11C7/1018 ,  G11C7/22

摘要： Burst SRAMs designed for operation at a given data rate corresponding to the frequency of a first clock signal but capable of operation using a higher frequency clock signal. The burst SRAMs are preferably incorporated into the cache memory of a second level cache coupled to the processor bus in a computer system, where the computer system is preferably based on a 66-MHz P5 microprocessor. A cache controller, preferably incorporated within a memory controller, controls operation of the second level cache memory by providing the address load and address advance signals. The burst SRAMs are capable of recognizing the faster clock pulses, as well as the shorter pulses asserted on the address load and address advance signals. The address control signals are asserted and then negated during consecutive clock cycles of the faster clock signal, so that the burst SRAMs effectively operate at the same data rate corresponding to the lower frequency clock signal.

摘要翻译： 突发SRAM设计用于以与第一时钟信号的频率对应的给定数据速率进行操作，但是能够使用较高频率的时钟信号进行操作。 突发SRAM优选地并入计算机系统中耦合到处理器总线的第二级高速缓冲存储器中，其中计算机系统优选地基于66MHz P5微处理器。 优选地结合在存储器控制器中的高速缓存控制器通过提供地址负载和地址提前信号来控制第二级高速缓冲存储器的操作。 突发SRAM能够识别更快的时钟脉冲，以及在地址负载和地址提前信号上断言的较短脉冲。 在更快的时钟信号的连续时钟周期期间，地址控制信号被断言然后被否定，使得脉冲串SRAM以与较低频率时钟信号对应的相同数据速率有效地工作。

公开(公告)号：EP0617364B1

公开(公告)日：2001-07-04

申请号：EP94302012.3

申请日：1994-03-22

申请人： Compaq Computer Corporation

发明人： Thome, Gary W.

IPC分类号： G06F12/14 ,  G06F13/16

CPC分类号： G06F13/1615 ,  G06F12/1491

公开(公告)号：EP0617364A2

公开(公告)日：1994-09-28

申请号：EP94302012.3

申请日：1994-03-22

申请人： Compaq Computer Corporation

发明人： Thome, Gary W.

IPC分类号： G06F12/14 ,  G06F13/16

CPC分类号： G06F13/1615 ,  G06F12/1491

摘要： A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices at their desired optimal speeds. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine reaches has completed its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory controller operates in system management mode to override any write protect status of memory so that the SMRAM can be located in the main memory space and be write protected during normal operations but be full usable during system management mode.

摘要翻译： 一个内存控制器，最大限度地利用任何处理器流水线并同时运行大量的周期。 存储器控制器可以以其期望的最佳速度利用不同的速度存储器件。 这些功能由多个简单的相互依赖的状态机执行，每个状态机负责整个操作的一小部分。 当每个状态机达到完成其功能时，它通知相关状态机现在可以继续进行，并继续等待下一个启动或继续指示。 下一台状态机以类似的方式运行。 负责一个周期的较早部分的状态机在下一个周期中开始执行任务，然后在负责周期的后期部分的状态机完成任务之前。 存储器控制器在逻辑上组织为三个主要块，前端块，存储块和主机块，每个都负责与其相关总线和组件的交互，并与各种其他块进行交互。 存储器控制器以系统管理模式操作以覆盖存储器的任何写保护状态，使得SMRAM可以位于主存储器空间中，并且在正常操作期间被写保护，但在系统管理模式期间可被完全使用。

公开(公告)号：EP0617365B1

公开(公告)日：2001-06-13

申请号：EP94302014.9

申请日：1994-03-22

申请人： Compaq Computer Corporation

发明人： Landry, John A. ,  Santeler, Paul A. ,  Thome, Gary W. ,  Bonella, Randy M. ,  Collins, Michael J.

IPC分类号： G06F13/16

CPC分类号： G06F13/1615

公开(公告)号：EP0707268A2

公开(公告)日：1996-04-17

申请号：EP95307349.1

申请日：1995-10-13

申请人： Compaq Computer Corporation

发明人： Stevens, Jeffrey C. ,  Thome, Gary W. ,  Larson, John E. ,  Collins, Michael J. ,  Moriarty, Michael

IPC分类号： G06F12/06

CPC分类号： G06F13/4243 ,  G06F13/1689 ,  G06F13/1694

摘要： A memory controller for a computer system provides a series of queues between the processor and a PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI-to-memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI-to-memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI-to-memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices. The memory controller includes a plurality of registers that specify number of clock periods for the particular portions of a conventional dynamic random access memory cycle which are used to control state machine operations.

摘要翻译： 用于在计算机系统的存储器控​​制器提供了一系列的处理器和PCI总线与存储器系统之间的线索。存储器一致性被保持在两种不同的方式。 之前任何读取操作从PCI总线所接受，无论是发布队列必须是空的。 内容可寻址存储器（CAM）被用作PCI到存储器队列中。 当处理器执行一个读请求时，所述CAM被检查以确定矿如果在PCI到存储器队列中的未决写操作中的一个是相同的地址作为处理器的读出手术。 这样读出的不可操作执行，直到PCI到存储器队列被清除写入如果。 要解决中止多重存储器读取手术问题的，中止从PCI总线接口信号被接收，此后只要可以做提前读周期结束，即使预读循环处理不当的全面完成。 存储器控制器具有改进的基于是否周期从处理器来或从PCI总线来允许更有效的预充电。当使用PCI总线周期的预测规则。 存储器控制器为多个速度和类型的处理器和存储器设备的几个速度高度可编程。 存储器控制器包括寄存器的多元性确实指定其用来控制状态机的操作的常规的动态随机存取存储器周期的特定部分的时钟周期的数目。

公开(公告)号：EP0617364A3

公开(公告)日：1995-10-11

申请号：EP94302012.3

申请日：1994-03-22

申请人： Compaq Computer Corporation

发明人： Thome, Gary W.

IPC分类号： G06F12/14 ,  G06F13/16

CPC分类号： G06F13/1615 ,  G06F12/1491

摘要： A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices at their desired optimal speeds. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine reaches has completed its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory controller operates in system management mode to override any write protect status of memory so that the SMRAM can be located in the main memory space and be write protected during normal operations but be full usable during system management mode.

公开(公告)号：EP0617367B1

公开(公告)日：1999-10-13

申请号：EP94302036.2

申请日：1994-03-22

申请人： Compaq Computer Corporation

发明人： Ayash, Basem Abu ,  Thome, Gary W.

IPC分类号： G06F13/24

CPC分类号： G06F9/4812 ,  G06F9/463 ,  G06F12/02 ,  G06F13/24

公开(公告)号：EP0707271A1

公开(公告)日：1996-04-17

申请号：EP95307345.9

申请日：1995-10-13

申请人： Compaq Computer Corporation

发明人： Thome, Gary W.

IPC分类号： G06F13/42 ,  G06F12/08

CPC分类号： G06F13/16 ,  G06F9/45533 ,  G06F12/0888 ,  G06F13/4243

摘要： A computer system which provides for slowing the effective speed of a microprocessor. The microprocessor includes a disabling input that when deactivated disables operations of the microprocessor on the processor bus. A computer system according to the invention periodically deasserts this signal with the certain duty cycle, allowing the microprocessor to continue to perform necessary functions at an effective rate compatible with older microprocessors, but never requiring an actual clock frequency change. This periodic deassertion is performed in response to a memory refresh counter that periodically counts down to zero and is reloaded. By comparing an input/output register with the refresh counter, and by adjusting the input/output register, the deasserting signal to the processor is periodically deasserted with a selectable duty cycle.

摘要翻译： 提供减慢微处理器有效速度的计算机系统。 微处理器包括禁用输入，当禁用时禁用处理器总线上的微处理器的操作。 根据本发明的计算机系统以一定的占空比周期性地消除该信号，允许微处理器以与旧的微处理器兼容的有效速率继续执行必要的功能，但是不需要实际的时钟频率变化。 响应于周期性地向下计数到零并被重新加载的存储器刷新计数器执行该周期性的取消忽略。 通过将输入/输出寄存器与刷新计数器进行比较，通过调整输入/输出寄存器，可以通过可选择的占空比周期性地解除对处理器的去激活信号。

公开(公告)号：EP0617367A3

公开(公告)日：1994-10-19

申请号：EP94302036.2

申请日：1994-03-22

申请人： Compaq Computer Corporation

发明人： Ayash, Basem Abu ,  Thome, Gary W.

IPC分类号： G06F13/24

CPC分类号： G06F9/4812 ,  G06F9/463 ,  G06F12/02 ,  G06F13/24

摘要： A system management mode address correction system for a computer provides correct address values on the address bus when the computer is in system management mode. Conventionally, bit 20 of the microprocessor's address outputs may be masked by asserting the FORCE A20 signal. The computer system also operates in a system management mode, which requires all of the address bits to be available for proper access to the system management interrupt vector. When the computer is in system management mode, the computer's microprocessor asserts a system management interrupt active (SMIACT*) signal. This signal is provided to a circuit which also receives the FORCE A20 signal. While the SMIACT signal is deactivated, the control circuit provides the true FORCE A20 signal to the computer system. When an SMI occurs, the SMIACT signal is activated and the FORCE A20 signal is disabled. As a result, the address generated by the microprocessor is asserted on the address bus.

摘要翻译： 当计算机处于系统管理模式时，计算机的系统管理模式地址校正系统在地址总线上提供正确的地址值。 通常，微处理器的地址输出的位20可以通过置位FORCE A20信号来屏蔽。 计算机系统也以系统管理模式运行，这要求所有的地址位可用于正确访问系统管理中断向量。 当计算机处于系统管理模式时，计算机的微处理器将激活系统管理中断激活（SMIACT *）信号。 该信号被提供给也接收FORCE A20信号的电路。 当SMIACT信号被禁用时，控制电路向计算机系统提供真实的FORCE A20信号。 发生SMI时，SMIACT信号被激活，FORCE A20信号被禁用。 结果，微处理器产生的地址在地址总线上被置位。

公开(公告)号：EP0617366A1

公开(公告)日：1994-09-28

申请号：EP94302037.0

申请日：1994-03-22

申请人： Compaq Computer Corporation

发明人： Santeler, Paul A. ,  Thome, Gary W.

IPC分类号： G06F13/16

CPC分类号： G06F9/3869 ,  G06F13/1615 ,  G06F13/1689

摘要： A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller utilizes different speed memory devices at each memory devices optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine reaches has completed its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory system includes a single chip which provides all of the address and control signals to a memory device so that a clock cycle can be saved because of reduced skew of the signals. The signals are provided synchronously from the chip.

摘要翻译： 一种存储器控制器，其最大限度地利用任何处理器流水线的和同时运行大量循环的。 存储器控制器在每个存储器装置最佳速度利用不同速度的存储器装置。 功能是通过简单，相互依存的状态机的复数，每个负责整个操作的一个小部分上执行。 由于每个状态机到达已经完成它的功能，它会通知相关的状态机做到了，现在可以继续并继续等待它的下一个启动或进行指示。 接下来的状态机采用了类似的方式。 负责周期的早期部分的状态机已经在下一个周期开始了他们的任务，负责周期的后期部分的状态机已经完成了他们的任务之前。 所述存储器控制器被逻辑地组织为三个主要的块，前端块，存储块和主机块，每个负责与其相关的总线和部件和各种其它块为握手相互作用的相互作用。 该存储器系统包括一个单一的芯片，所有的地址和控制信号的提供到存储器设备，以便做一个时钟周期可以由于减少了信号的歪斜被保存。 的信号从芯片同步提供。