-
1.发明公开Apparatus for direct memory-to-memory intercomputer communication 失效Gerätzur direkten Speicher-zu-Speicherübertragungzwischen Rechnern。
公开(公告)号：EP0094177A2
公开(公告)日：1983-11-16
申请号：EP83302411.0
申请日：1983-04-28
IPC分类号： G06F15/16
CPC分类号： G06F15/167 , G06F15/177
摘要： Method and apparatus for transfer of packet-type information from the memory (24B) of one node (14) in a computer network to the memory (24C) of another node (16) in the network. The invention is of particular utility in transfers over serial buses (e.g., 18). Packets are sent from a named memory buffer (25A) at a first node (14) to a named memory buffer (25C) at a second node (16), allowing random access by the first node to the memory of the second node without either node having to have knowledge of the memory structure of the other; the source and destination buffer names are contained right in the transmitted packet.
The first node (14) can both write to and read from the second node (16). An opcode (40A) sent in each packet signifies whether a read or write operation is to be performed. For reading from the second node, the opcode actually causes the second node to write back to the first node; in this situation, the second node to write back to the first node; in this situation, che second node, upon detecting the appropriate opcode, places the remainder of the received packet on a command queue (202), to be excuted with the commands locally generated at the second node, without need for host interruption.摘要翻译： 将分组类型信息从计算机网络中的一个节点（14）的存储器（24B）传送到网络中另一个节点（16）的存储器（24C）的方法和装置。 本发明在通过串行总线（例如，18）的传输中特别有用。 分组在第一节点（14）处从命名的存储器缓冲器（25A）发送到第二节点（16）处的命名存储器缓冲器（25C），允许第一节点随机访问第二节点的存储器，而无需任何 节点必须知道另一个的存储器结构; 源和目标缓冲区名称直接包含在传输的数据包中。 第一节点（14）可以向第二节点（16）写入和读取。 在每个分组中发送的操作码（40A）表示是否执行读或写操作。 为了从第二节点读取，操作码实际上使第二节点回写到第一节点; 在这种情况下，第二个节点要回写到第一个节点; 在这种情况下，第二节点在检测到适当的操作码时，将接收到的分组的剩余部分置于命令队列（202）上，以便在第二节点处本地生成的命令被排除，而不需要主机中断。
-
公开(公告)号：EP0340347A2
公开(公告)日：1989-11-08
申请号：EP88200854.3
申请日：1984-09-21
IPC分类号： G06F13/374
CPC分类号： G06F13/374
摘要： The invention relates to a device adapted to be connected to a non-pended bus, a circuit of this device for providing communications interface for that device to the non-pended bus, and a process by which this device arbitrates an access to a bus.
The interconnecting circuit comprises controller means (300) coupled to a no arbitration and busy lines of the bus for indicating an arbitration cycle, driver means (334) coupled to the controller means for asserting one or two data lines of the bus corresponding to the device during the arbitration, priority resolution means (380) coupled to the data lines to indicate that the device has the highest priority during the arbitration cycle, receive register means (304) coupled to information lines of the bus for comparing the ID number of the device with the ID number of the device, and switching means (308) connected to receive register and to driver means for asserting low or high priority data line to the device during the arbitration cycle.摘要翻译： 本发明涉及一种适用于连接到非正交总线的设备，该设备的电路用于向该非设备总线提供该设备的通信接口，以及该设备通过该设备仲裁访问总线的过程。 互连电路包括耦合到总线的无仲裁和忙线以指示仲裁周期的控制器装置（300），耦合到控制器装置的驱动装置（334），用于断言对应于装置的总线的一条或两条数据线 在仲裁期间，优先权解析装置（380）耦合到数据线以指示在仲裁周期期间该设备具有最高优先权;接收寄存器装置（304），耦合到总线的信息线，用于比较装置的ID号 以及连接到接收寄存器的切换装置（308）和用于在仲裁周期期间向设备断言低或高优先级的数据线的驱动器装置。
-
公开(公告)号：EP0094179A3
公开(公告)日：1985-01-30
申请号：EP83302413
申请日：1983-04-28
CPC分类号： G06F11/2007 , G06F11/22 , G06F13/36 , G06F13/4022
摘要： A bus structure for use in a computer network requiring high availability and reliability of communications. Multiple bus paths (2A, 2B) are provided. When a transmission is to be made, under most circumstances the path is selected at random, with all paths being equally probable. Thus, failure of a path is detected quickly. Each host device in the network connects to the bus paths through an interface, or port (1). The task of path selection is carried out by the ports, independently of the host devices. The ports also detect path failures and automatically switch over to an alternate good path upon detection of such a failure, all without host involvement. Virtual circuit communications between hosts are transparent to path selection and switching, so the only indication to a host device of a path failure is a decrease in throughput. Most of the signal processing apparatus of each port (10, 20A, 20B) is shared by the paths, only one path being supported at any given time. Thus, the addition of a second bus path involves only minimal cost.
-
公开(公告)号：EP0094179A2
公开(公告)日：1983-11-16
申请号：EP83302413.6
申请日：1983-04-28
CPC分类号： G06F11/2007 , G06F11/22 , G06F13/36 , G06F13/4022
摘要： A bus structure for use in a computer network requiring high availability and reliability of communications. Multiple bus paths (2A, 2B) are provided. When a transmission is to be made, under most circumstances the path is selected at random, with all paths being equally probable. Thus, failure of a path is detected quickly.
Each host device in the network connects to the bus paths through an interface, or port (1). The task of path selection is carried out by the ports, independently of the host devices. The ports also detect path failures and automatically switch over to an alternate good path upon detection of such a failure, all without host involvement. Virtual circuit communications between hosts are transparent to path selection and switching, so the only indication to a host device of a path failure is a decrease in throughput.
Most of the signal processing apparatus of each port (10, 20A, 20B) is shared by the paths, only one path being supported at any given time. Thus, the addition of a second bus path involves only minimal cost.摘要翻译： 一种用于需要高可用性和通信可靠性的计算机网络中的总线结构。 提供多个总线路径（2A，2B）。 当要进行传输时，在大多数情况下，随机选择路径，所有路径都是同等可能的。 因此，快速检测路径的故障。 网络中的每个主机设备通过接口或端口（1）连接到总线路径。 路由选择的任务由端口执行，独立于主机设备。 这些端口还检测到路径故障，并且在检测到这样的故障时自动切换到备用的良好路径，所有这些都没有主机参与。 主机之间的虚拟电路通信对于路径选择和切换是透明的，因此对主机设备进行路径故障的唯一指示是吞吐量的降低。 每个端口（10,20A，20B）的信号处理设备的大部分由路径共享，在任何给定时间仅支持一条路径。 因此，添加第二总线路径只需要最小的成本。
-
公开(公告)号：EP0340347A3
公开(公告)日：1990-03-14
申请号：EP88200854.3
申请日：1984-09-21
IPC分类号： G06F13/374
CPC分类号： G06F13/374
摘要： The invention relates to a device adapted to be connected to a non-pended bus, a circuit of this device for providing communications interface for that device to the non-pended bus, and a process by which this device arbitrates an access to a bus. The interconnecting circuit comprises controller means (300) coupled to a no arbitration and busy lines of the bus for indicating an arbitration cycle, driver means (334) coupled to the controller means for asserting one or two data lines of the bus corresponding to the device during the arbitration, priority resolution means (380) coupled to the data lines to indicate that the device has the highest priority during the arbitration cycle, receive register means (304) coupled to information lines of the bus for comparing the ID number of the device with the ID number of the device, and switching means (308) connected to receive register and to driver means for asserting low or high priority data line to the device during the arbitration cycle.
-
6.发明公开Apparatus and method for improving system bus performance in a data processng system 失效装置和用于改进数据处理设备的系统性能的方法。
公开(公告)号：EP0192366A2
公开(公告)日：1986-08-27
申请号：EP86300658.1
申请日：1986-01-31
CPC分类号： G06F13/36 , G06F12/084 , G06F12/0846 , G06F12/0851 , G06F13/362 , G06F13/4217
摘要： In a data.processing system in which a plurality of data processing units, as well as the main memory unit, are coupled to a system bus, the utilization of the system bus is Increased to such an extent that each of a plurality of cache memory units coupled to the system bus can have a plurality of data processing units associated therewith. The system bus utilization is increased by dividing the system bus access operation into a plurality of sub-operations and by providing a defined cyclic sequence for the cache memory units to have access to the system bus.
摘要翻译： 在其中的数据处理单元复数，以及主存储器单元，被耦合到系统总线的数据处理系统，该系统总线的利用率可提高到上程度搜索没有每个高速缓存存储器中的多个 耦合到系统总线单元可以具有连接到其上的数据处理单元的多元性。 系统总线利用率是通过将系统总线访问手术进入子操作的多个部分并加以通过提供一种用于在高速缓冲存储器单元的定义循环序列能够访问系统总线增加。 该系统总线被分成的子总线单元的多元性来处理数据传输的单独的功能。 主存储单元具有用于写 - 修改 - 读操作的效率的执行装置。 此外，高速缓冲存储器单元可以被分成子单元的多元化和接入到在高速缓冲存储器子单元的环状准入方面布置在系统总线。
-
7.发明公开Arbitration mechanism for assigning control of a communications path in a digital computer system 失效仲裁控制在数字计算机系统中的传输路径的分配。
公开(公告)号：EP0139569A2
公开(公告)日：1985-05-02
申请号：EP84401884.6
申请日：1984-09-21
IPC分类号： G06F13/36
CPC分类号： G06F13/374
摘要： Devices for interconnection into a digital computer system contain arbitration mechanisms for assigning control of a common communications path among the devices. Several modes of device arbitration are provided for, and the modes may be mixed among devices, and changed during operation of the system, in the system without interfering with communications. The arbitration mechanism requires only a single additional line in the communications pathway, and thus a single additional pin on the integrated circuit on which it is implemented, for the arbitration function. It thus facilitates implementation of the arbitration mechanism along with all other interconnect logic on a single integrated circuit.
-
8.发明公开Method and apparatus for direct memory-to-memory intercomputer communication 失效用于直接存储器到存储器间通信通信的方法和装置
公开(公告)号：EP0094177A3
公开(公告)日：1985-01-09
申请号：EP83302411
申请日：1983-04-28
IPC分类号： G06F15/16
CPC分类号： G06F15/167 , G06F15/177
摘要： Method and apparatus for transfer of packet-type information from the memory (24B) of one node (14) in a computer network to the memory (24C) of another node (16) in the network. The invention is of particular utility in transfers over serial buses (e.g., 18). Packets are sent from a named memory buffer (25A) at a first node (14) to a named memory buffer (25C) at a second node (16), allowing random access by the first node to the memory of the second node without either node having to have knowledge of the memory structure of the other; the source and destination buffer names are contained right in the transmitted packet. The first node (14) can both write to and read from the second node (16). An opcode (40A) sent in each packet signifies whether a read or write operation is to be performed. For reading from the second node, the opcode actually causes the second node to write back to the first node; in this situation, the second node to write back to the first node; in this situation, che second node, upon detecting the appropriate opcode, places the remainder of the received packet on a command queue (202), to be excuted with the commands locally generated at the second node, without need for host interruption.
-
公开(公告)号：EP0340347B1
公开(公告)日：1994-04-06
申请号：EP88200854.3
申请日：1984-09-21
IPC分类号： G06F13/374
CPC分类号： G06F13/374
-
公开(公告)号：EP0094177B1
公开(公告)日：1989-07-12
申请号：EP83302411.0
申请日：1983-04-28
IPC分类号： G06F15/16
CPC分类号： G06F15/167 , G06F15/177
-
-
-
-
-
-
-
-
-
搜索结果
19 条记录 (耗时 0.016 秒)
