公开(公告)号：EP2863440A1

公开(公告)日：2015-04-22

申请号：EP13804906.9

申请日：2013-06-06

申请人： Denso Corporation ,  Toyota Jidosha Kabushiki Kaisha

发明人： TAKEUCHI, Yuichi ,  SUZUKI, Naohiro ,  SOEJIMA, Narumasa ,  WATANABE, Yukihiko ,  SUGIMOTO, Masahiro ,  TAKAYA, Hidefumi ,  SOENO, Akitaka ,  MORIMOTO, Jun

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L27/04 ,  H01L29/06 ,  H01L29/12 ,  H01L29/47 ,  H01L29/861 ,  H01L29/868 ,  H01L29/872

CPC分类号： H01L29/7811 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/761 ,  H01L21/8213 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/157 ,  H01L29/158 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

摘要： An SiC semiconductor device has a p type region (5) including a low concentration region (5b) and a high concentration region (5c) filled in a trench (5a) formed in a cell region. A p type column is provided by the low concentration region (5b), and a p + type deep layer is provided by the high concentration region (5c). Thus, since a SJ structure can be made by the p type column provided by the low concentration region (5b) and the n type column provided by the n type drift layer (2), an on-state resistance can be reduced. Since a drain potential can be blocked by the p + type deep layer provided by the high concentration region (5c), at a time of turning off, an electric field applied to the gate insulation film (8) can be alleviated and thus breakage of the gate insulation film (8) can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film (8).

摘要翻译： SiC半导体器件具有包括填充在单元区域中形成的沟槽（5a）中的低浓度区域（5b）和高浓度区域（5c）的p型区域（5）。 低浓度区（5b）提供p型柱，高浓度区（5c）提供p +型深层。 因此，由于可以通过由低浓度区域（5b）提供的p型列和由n型漂移层（2）提供的n型列来形成SJ结构，所以可以降低导通电阻。 由于漏极电位能够被高浓度区域（5c）提供的p +型深层阻挡，所以在关断时，可以减轻施加到栅极绝缘膜（8）的电场，并因此破坏 栅绝缘膜（8）可以被限制。 因此，SiC半导体器件可以实现导通电阻的降低和栅极绝缘膜（8）的断裂限制。

公开(公告)号：EP3308392A1

公开(公告)日：2018-04-18

申请号：EP16731351.9

申请日：2016-06-03

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA ,  Denso Corporation

发明人： TAKAYA, Hidefumi ,  MIZUNO, Shoji ,  WATANABE, Yukihiko ,  AOI, Sachiko

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/12 ,  H01L29/06 ,  H01L29/423

CPC分类号： H01L29/1608 ,  H01L21/02529 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

摘要： A method for manufacturing an insulated gate switching device is provided. The method includes: forming a first trench in a surface of a first SiC semiconductor layer; implanting p-type impurities into a bottom surface of the first trench; depositing a second SiC semiconductor layer on an inner surface of the first trench to form a second trench; and forming a gate insulating layer, a gate electrode, a first region and a body region so that the gate insulating layer covers an inner surface of the second trench, the gate electrode is located in the second trench, the first region is of n-type and in contact with the gate insulating layer, the body region is of p-type, separated from the implanted region, and in contact with the gate insulating layer under the first region.

公开(公告)号：EP2863417A1

公开(公告)日：2015-04-22

申请号：EP13804396.3

申请日：2013-06-06

申请人： DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

发明人： TAKEUCHI, Yuichi ,  SOEJIMA, Narumasa ,  WATANABE, Yukihiko ,  CHIDA, Kazumi

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/12 ,  H01L29/78

CPC分类号： H01L29/66068 ,  H01L21/02529 ,  H01L21/0455 ,  H01L21/0475 ,  H01L21/049 ,  H01L21/3065 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827

摘要： In a method for producing an SiC semiconductor device, a p type layer (31) is formed in a trench (6) by epitaxially growing, and is then left only on a bottom portion and ends of the trench by hydrogen etching, thereby to form a p type SiC layer (7). That is, a portion of the p type layer (31) formed on a side surface of the trench (6) is removed. Thus, the p type SiC layer (7) can be formed without depending on diagonal ion implantation. Since it is not necessary to separately perform the diagonal ion implantation, it is less likely that a production process will be complicated due to transferring into an ion implantation apparatus, and thus manufacturing costs reduce. Since there is no damage due to a defect caused by the ion implantation, it is possible to reduce a drain leakage and to reliably restrict the p type SiC layer (7) from remaining on the side surface of the trench (6). Accordingly, it is possible to produce an SiC semiconductor device that can achieve both high withstand voltage and high switching speed.

摘要翻译： 在用于制造SiC半导体器件的方法中，通过外延生长在沟槽（6）中形成p型层（31），然后通过氢蚀刻仅留在沟槽的底部和端部上，从而形成p 型SiC层（7）。 即，形成在沟槽（6）的侧表面上的p型层（31）的一部分被去除。 因此，可以在不依赖于对角离子注入的情况下形成p型SiC层（7）。 由于不需要单独进行对角线离子注入，因此由于转移到离子注入装置而使生产过程变得复杂的可能性较小，因此制造成本降低。 由于没有因离子注入引起的缺陷而造成损坏，所以可以减少漏极泄漏并且可靠地限制p型SiC层（7）保留在沟槽（6）的侧表面上。 因此，可以制造既能实现高耐压又能实现高开关速度的SiC半导体器件。