公开(公告)号：EP2863440A1

公开(公告)日：2015-04-22

申请号：EP13804906.9

申请日：2013-06-06

申请人： Denso Corporation ,  Toyota Jidosha Kabushiki Kaisha

发明人： TAKEUCHI, Yuichi ,  SUZUKI, Naohiro ,  SOEJIMA, Narumasa ,  WATANABE, Yukihiko ,  SUGIMOTO, Masahiro ,  TAKAYA, Hidefumi ,  SOENO, Akitaka ,  MORIMOTO, Jun

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L27/04 ,  H01L29/06 ,  H01L29/12 ,  H01L29/47 ,  H01L29/861 ,  H01L29/868 ,  H01L29/872

CPC分类号： H01L29/7811 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/761 ,  H01L21/8213 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/157 ,  H01L29/158 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

摘要： An SiC semiconductor device has a p type region (5) including a low concentration region (5b) and a high concentration region (5c) filled in a trench (5a) formed in a cell region. A p type column is provided by the low concentration region (5b), and a p + type deep layer is provided by the high concentration region (5c). Thus, since a SJ structure can be made by the p type column provided by the low concentration region (5b) and the n type column provided by the n type drift layer (2), an on-state resistance can be reduced. Since a drain potential can be blocked by the p + type deep layer provided by the high concentration region (5c), at a time of turning off, an electric field applied to the gate insulation film (8) can be alleviated and thus breakage of the gate insulation film (8) can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film (8).

摘要翻译： SiC半导体器件具有包括填充在单元区域中形成的沟槽（5a）中的低浓度区域（5b）和高浓度区域（5c）的p型区域（5）。 低浓度区（5b）提供p型柱，高浓度区（5c）提供p +型深层。 因此，由于可以通过由低浓度区域（5b）提供的p型列和由n型漂移层（2）提供的n型列来形成SJ结构，所以可以降低导通电阻。 由于漏极电位能够被高浓度区域（5c）提供的p +型深层阻挡，所以在关断时，可以减轻施加到栅极绝缘膜（8）的电场，并因此破坏 栅绝缘膜（8）可以被限制。 因此，SiC半导体器件可以实现导通电阻的降低和栅极绝缘膜（8）的断裂限制。

公开(公告)号：EP3308392A1

公开(公告)日：2018-04-18

申请号：EP16731351.9

申请日：2016-06-03

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA ,  Denso Corporation

发明人： TAKAYA, Hidefumi ,  MIZUNO, Shoji ,  WATANABE, Yukihiko ,  AOI, Sachiko

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/12 ,  H01L29/06 ,  H01L29/423

CPC分类号： H01L29/1608 ,  H01L21/02529 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

摘要： A method for manufacturing an insulated gate switching device is provided. The method includes: forming a first trench in a surface of a first SiC semiconductor layer; implanting p-type impurities into a bottom surface of the first trench; depositing a second SiC semiconductor layer on an inner surface of the first trench to form a second trench; and forming a gate insulating layer, a gate electrode, a first region and a body region so that the gate insulating layer covers an inner surface of the second trench, the gate electrode is located in the second trench, the first region is of n-type and in contact with the gate insulating layer, the body region is of p-type, separated from the implanted region, and in contact with the gate insulating layer under the first region.

公开(公告)号：EP1671374B1

公开(公告)日：2018-05-09

申请号：EP04792407.1

申请日：2004-10-06

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA

发明人： TAKAYA, Hidefumi ,  HAMADA, Kimimori ,  KUROYANAGI, Akira ,  OKURA, Yasushi ,  TOKURA, Norihito

IPC分类号： H01L29/78 ,  H01L29/739 ,  H01L29/06 ,  H01L29/423 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/7397 ,  H01L29/7811

摘要： The invention is intended to present an insulated gate type semiconductor device that can be manufactured easily and its manufacturing method while realizing both higher withstand voltage design and lower on-resistance design. The semiconductor device comprises N+ source region 31, N+ drain region 11, P- body region 41, and N- drift region 12. By excavating part of the upper side of the semiconductor device, a gate trench 21 is formed. The gate trench 21 incorporates the gate electrode 22. A P floating region 51 is provided beneath the gate trench 21. A further trench 35 differing in depth from the gate trench 21 may be formed, a P floating region 54 being provided beneath the trench 25.

公开(公告)号：EP1994566B1

公开(公告)日：2018-01-17

申请号：EP07707920.0

申请日：2007-01-26

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA

发明人： TAKAYA, Hidefumi ,  HAMADA, Kimimori ,  MIYAGI, Kyosuke

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L21/265

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor 100 has a P− body region and an N− drift region in the order from an upper surface side thereof. A gate trench and a terminal trench passing through the P− body region are formed. The respective trenches are surrounded with P diffusion regions at the bottom thereof. The gate trench builds a gate electrode therein. A P−− diffusion region, which is in contact with the end portion in a lengthwise direction of the gate trench and is lower in concentration than the P− body region and the P diffusion region, is formed. The P−− diffusion region is depleted prior to the P diffusion region when the gate voltage is off. The P−− diffusion region serves as a hole supply path to the P diffusion region when the gate voltage is on.

公开(公告)号：EP1994566A1

公开(公告)日：2008-11-26

申请号：EP07707920.0

申请日：2007-01-26

申请人： Toyota Jidosha Kabushiki Kaisha

发明人： TAKAYA, Hidefumi ,  HAMADA, Kimimori ,  MIYAGI, Kyosuke

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L21/265

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor 100 has a P− body region and an N− drift region in the order from an upper surface side thereof. A gate trench and a terminal trench passing through the P− body region are formed. The respective trenches are surrounded with P diffusion regions at the bottom thereof. The gate trench builds a gate electrode therein. A P−− diffusion region, which is in contact with the end portion in a lengthwise direction of the gate trench and is lower in concentration than the P− body region and the P diffusion region, is formed. The P−− diffusion region is depleted prior to the P diffusion region when the gate voltage is off. The P−− diffusion region serves as a hole supply path to the P diffusion region when the gate voltage is on.

公开(公告)号：EP4307382A1

公开(公告)日：2024-01-17

申请号：EP21930302.1

申请日：2021-11-05

申请人： DENSO CORPORATION

发明人： TAKAYA, Hidefumi

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/12 ,  H01L21/336

摘要： Afield effect transistor 10 includes a p-type trench lower layer 35, multiple p-type deep layers 36, and multiple n-type deep layers 37. The p-type trench lower layer is located below the trench 14, and extends in a longitudinal direction of the trench in a top view of a semiconductor substrate 12. Each of the p-type deep layers protrudes downward from a body layer 34, and extends in a first direction intersecting the trench in the top view of the semiconductor substrate. The p-type deep layers are spaced at intervals in a second direction perpendicular to the first direction, and are in contact with the p-type trench lower layer located below the trench. Each of the n-type deep layers is located in corresponding one of the intervals, and is in contact with a gate insulating film at a side surface of the trench located below the body layer.