公开(公告)号：EP1579495A2

公开(公告)日：2005-09-28

申请号：EP03814808.6

申请日：2003-12-16

申请人： Easic Corporation

发明人： OR-BACH, Zvi ,  COOKE, Laurence ,  APOSTOL, Adrian ,  IACOBUT, Romeo

IPC分类号： H01L21/44 ,  H01L23/34 ,  H01L27/10

CPC分类号： H01L28/20 ,  H01L23/3114 ,  H01L24/10 ,  H01L27/11803 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/051 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/05005 ,  H01L2224/05541 ,  H01L2924/00014

摘要： A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I/Os (36) and also including the step of forming redistribution layer (32) for redistribution at least some of the Area I/Os for the purpose of the device packaging. The fabrication may utilize Direct Write e-Beam for customization. The customization step may include fabricating various types of devices at different volume from the same wafer.