公开(公告)号：EP3341956A1

公开(公告)日：2018-07-04

申请号：EP16840097.6

申请日：2016-08-25

Applicant: Invensas Bonding Technologies, Inc.

Inventor： ENQUIST, Paul, M.

IPC: H01L21/18 ,  H01L21/52 ,  H01L23/00

CPC classification number: H01L24/09 ,  H01L21/50 ,  H01L24/03 ,  H01L24/80 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/036 ,  H01L2224/05005 ,  H01L2224/05078 ,  H01L2224/05082 ,  H01L2224/08145 ,  H01L2224/8019 ,  H01L2224/80895 ,  H01L2225/06513

Abstract: A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.

公开(公告)号：EP3126065A2

公开(公告)日：2017-02-08

申请号：EP15741878.1

申请日：2015-03-31

Applicant: Koninklijke Philips N.V.

Inventor： JACOBS, Egbertus Reinier ,  WEEKAMP, Johannes Wilhelmus ,  RIJKERS, Niels Cornelis Wilhelmus Johannes

IPC: B06B1/02 ,  A61B8/00 ,  H01L23/00 ,  A61B8/12

CPC classification number: B06B1/0292 ,  A61B8/12 ,  A61B8/445 ,  A61B8/4494 ,  H01L21/78 ,  H01L24/01 ,  H01L24/03 ,  H01L24/06 ,  H01L41/0475 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0362 ,  H01L2224/05005 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2924/1433 ,  H01L2924/2064 ,  H01L2924/20641 ,  H02N1/006 ,  H05K1/181 ,  H05K2201/10151

Abstract: An integrated circuit (IC) die (100) is disclosed having a major surface delimited by at least one edge (102) of the IC die, said major surface carrying a plurality of electrically conductive contact plates (130) extending from said major surface beyond the at least one edge such that each contact plate includes an exposed contact surface portion (132) delimited by the at least one edge for mating with an electrically conductive further contact surface portion (230) on at least one further edge (220) of a body (200), said at least one further edge delimiting a cavity for receiving the IC die. An ultrasound probe including such an IC die and a method of providing such an IC die with contacts are also disclosed.

Abstract translation: 公开了一种集成电路（IC）管芯（100），其具有由IC管芯的至少一个边缘（102）限定的主表面，所述主表面承载从所述主表面延伸超过的多个导电接触板（130） 所述至少一个边缘使得每个接触板包括由所述至少一个边缘限定的暴露的接触表面部分（132），用于与所述至少一个边缘的至少一个另外的边缘（220）配合的导电的另外的接触表面部分（230） 所述至少一个另外的边缘限定用于容纳IC管芯的空腔。 还公开了一种包括这种IC芯片的超声波探头以及提供具有触点的IC芯片的方法。

公开(公告)号：EP1351285A3

公开(公告)日：2006-12-27

申请号：EP03251979.5

申请日：2003-03-28

Applicant: Hewlett-Packard Company

Inventor： Liebeskind, John ,  McKinnell, James C. ,  Benning, Paul J. ,  Chen, Chien-Hua

IPC: H01L21/60 ,  B81B7/00

CPC classification number: H01L25/50 ,  B81B7/0006 ,  H01L21/50 ,  H01L23/10 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/16105 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06565 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05541 ,  H01L2224/05005

Abstract: An electrical device (100, 502, 602, 702) includes a plurality of integrated circuits (106) respectively fabricated in a first substrate (102) bonded to a second substrate (104) by a bond (111) that deforms above, but not below, a deformation condition. The deformation condition can be a predetermined pressure from opposing surfaces on the first and second substrates (102, 104) or is can be a predetermined combination of temperature and pressure from opposing surfaces on the first and second substrates (102, 104).

公开(公告)号：EP1527479A1

公开(公告)日：2005-05-04

申请号：EP03783921.4

申请日：2003-07-25

Applicant: Osram Opto Semiconductors GmbH

Inventor： KRÄUTER, Gertrud ,  SORG, Jörg, Erich

IPC: H01L23/495 ,  H01L23/498

CPC classification number: H01L23/48 ,  H01L23/495 ,  H01L23/498 ,  H01L24/73 ,  H01L24/97 ,  H01L33/00 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/12041 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: The invention relates to a method for the production of an electrically conducting frame (10), in particular for a light diode component, with at least one first (2) and one second electrical connection conductor (3). The method comprises the following steps: a) production of a layer composite made from an electrically-insulating support layer (101) and an electrically-conducting connection conductor layer (102), b) structuring the support layer (101) such that at least one contact window (7) facing the connection conductor layer (102) is generated therein, c) structuring the connection conductor layer (102) such that the first (2) and the second electrical connection conductor (3) are generated, of which at least one may be electrically connected through the contacting window (7). The invention further relates to a conductor frame strip with a connection conductor layer and connector support layer, upon which a field with a number of component regions is embodied, whereby the connection conductor layer is at least partly removed along separation lines between two adjacent component regions.

公开(公告)号：EP1152464A2

公开(公告)日：2001-11-07

申请号：EP01110351.2

申请日：2001-04-26

Applicant: SONY CORPORATION

Inventor： Nishiyama, Kazuo, c/o Sony Corporation

IPC: H01L23/31 ,  H01L21/68

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L23/3114 ,  H01L24/48 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/6834 ,  H01L2224/02166 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05571 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/274 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/05541 ,  H01L2224/05005 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In order to have a thin type semiconductor chips featuring a high yield and a low cost in production, an excellent packaging reliability, and a robust structure against damages, there is provided a method of manufacturing LSI chips, comprising the steps of: pasting on a substrate an adhesive sheet which retains its adhesive strength prior to a processing, then loses it after the processing; bonding non-defective LSI chips on the adhesive sheet, with their device surfaces facing downward; uniformly coating an insulating film on the non-defective LSI chips; uniformly grinding the insulating film to a level of the bottom surfaces of these LSI chips; applying a predetermined process to the adhesive sheet to weaken its adhesive strength thereof so as to peel off a pseudo wafer on which the non-defective LSI chips are bonded; and dicing the LSI chips into a discrete non-defective electronic component by cutting the pseudo wafer.

Abstract translation: 为了制造具有高产率和低成本的薄型半导体芯片，具有良好的封装可靠性和抗损坏的坚固结构，提供了一种制造LSI芯片的方法，包括以下步骤：粘贴在 基材是在加工前保持其粘合强度的粘合片，然后在加工后失去它; 将无缺陷的LSI芯片粘合在粘合片上，使其装置表面朝下; 在无缺陷的LSI芯片上均匀涂覆绝缘膜; 将绝缘膜均匀研磨到这些LSI芯片的底面的一个层面; 对粘合片施加预定的处理以削弱其粘合强度，以剥离其上粘合有缺陷的LSI芯片的伪晶片; 并通过切割伪晶片将LSI芯片切割成离散的无缺陷电子部件。

公开(公告)号：EP2471096A4

公开(公告)日：2015-04-29

申请号：EP10824354

申请日：2010-10-21

Applicant: ATI TECHNOLOGIES ULC

Inventor： TOPACIO RODEN ,  WONG GABRIEL

IPC: H01L23/485 ,  H01L21/60

CPC classification number: H01L23/49816 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05012 ,  H01L2224/05013 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05022 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05559 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05599 ,  H01L2224/06131 ,  H01L2224/1132 ,  H01L2224/13007 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/00 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/0105 ,  H01L2924/01083 ,  H01L2924/01028 ,  H01L2924/01031 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00012

Abstract: A routing layer for a semiconductor die is disclosed. The routing layer includes pads for attaching solder bumps; bond-pads bonded to bump-pads of a die having an integrated circuit, and traces interconnecting bond-pads to pads. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces at least partially surrounding some pads so as to absorb stress from solder bumps attached to the pads. Parts of the traces that surround pads protect parts of the underlying dielectric material proximate the solder bumps, from the stress.

Abstract translation: 公开了一种用于半导体管芯的布线层。 布线层包括用于附接焊料凸块的焊盘; 键合焊盘结合到具有集成电路的管芯的凸点焊盘，以及将互连的接合焊盘迹迹到焊盘。 布线层形成在介电材料层上。 路由层包括至少部分地围绕一些焊盘的导电迹线，以便吸收附着在焊盘上的焊料凸块的应力。 围绕焊盘的迹线的一部分保护靠近焊料凸块的基底电介质材料的部分免受应力的影响。

公开(公告)号：EP2775511A1

公开(公告)日：2014-09-10

申请号：EP11875240.1

申请日：2011-10-31

Applicant: Hitachi, Ltd.

Inventor： TANIE, Hisashi ,  SHINTANI, Hiroshi ,  TANAKA, Naotaka

IPC: H01L21/60 ,  H05K1/18

CPC classification number: H01L23/562 ,  H01L21/52 ,  H01L23/36 ,  H01L23/3736 ,  H01L23/488 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/83 ,  H01L2224/03444 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05005 ,  H01L2224/05011 ,  H01L2224/05016 ,  H01L2224/05023 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05655 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/11444 ,  H01L2224/1146 ,  H01L2224/13005 ,  H01L2224/13011 ,  H01L2224/13017 ,  H01L2224/13078 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/27444 ,  H01L2224/2745 ,  H01L2224/2746 ,  H01L2224/29005 ,  H01L2224/29011 ,  H01L2224/29017 ,  H01L2224/29078 ,  H01L2224/2908 ,  H01L2224/30181 ,  H01L2224/32105 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/3701 ,  H01L2224/37147 ,  H01L2224/38 ,  H01L2224/40095 ,  H01L2224/40106 ,  H01L2224/40229 ,  H01L2224/4103 ,  H01L2224/41176 ,  H01L2224/73204 ,  H01L2224/8309 ,  H01L2224/83101 ,  H01L2224/8321 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2224/29155 ,  H01L2224/29147 ,  H01L2924/00012 ,  H01L2224/291 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device has a packaging structure in which a top surface of a semiconductor chip 1 is electrically connected to a conductive member 4 through a deformation absorption layer 2a and a joining layer 3a and a bottom surface thereof is electrically connected to a conductive member 5 through a deformation absorption layer 2b and a joining layer 3b. Each of the deformation absorption layers 2a and 2b includes a nano-structure layer 7 arranged at a center of a thickness direction and plate layers 6 and 8 of two layers with the nano-structure layer 7 therebetween. The nano-structure layer 7 has a structure in which a plurality of nano-structures 9 having a size of 1 µm or less are two-dimensionally arranged and thermal stress due to a thermal deformation difference of each member forming the semiconductor device is absorbed by deformation of the nano-structures 9.

Abstract translation: 半导体器件具有封装结构，其中半导体芯片1的顶表面通过变形吸收层2a和接合层3a电连接到导电构件4，并且其底表面通过变形吸收层2a和接合层3a电连接到导电构件5 变形吸收层2b和接合层3b。 每个变形吸收层2a和2b包括布置在厚度方向的中心处的纳米结构层7和其间具有纳米结构层7的两层的板层6和8。 纳米结构层7具有其中二维排列具有1μm或更小尺寸的多个纳米结构9的结构，并且由于形成半导体器件的每个构件的热变形差异所引起的热应力被吸收 纳米结构9的变形。

公开(公告)号：EP2471096A1

公开(公告)日：2012-07-04

申请号：EP10824354.4

申请日：2010-10-21

Applicant: ATI Technologies ULC

Inventor： TOPACIO, Roden ,  WONG, Gabriel

IPC: H01L23/488 ,  H01L23/50

CPC classification number: H01L23/49816 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05012 ,  H01L2224/05013 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05022 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05559 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05599 ,  H01L2224/06131 ,  H01L2224/1132 ,  H01L2224/13007 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/00 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/0105 ,  H01L2924/01083 ,  H01L2924/01028 ,  H01L2924/01031 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00012

Abstract: A routing layer for a semiconductor die is disclosed. The routing layer includes pads for attaching solder bumps; bond-pads bonded to bump-pads of a die having an integrated circuit, and traces interconnecting bond-pads to pads. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces at least partially surrounding some pads so as to absorb stress from solder bumps attached to the pads. Parts of the traces that surround pads protect parts of the underlying dielectric material proximate the solder bumps, from the stress.

公开(公告)号：EP0991119B1

公开(公告)日：2006-05-17

申请号：EP98921896.1

申请日：1998-05-28

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： SHIMOISHIZAKA, Nozomi ,  SAHARA, Ryuichi ,  NAKAMURA, Yoshifumi ,  KUMAKAWA, Takahiro ,  MURAKAMI, Shinji ,  HARADA, Yukata

IPC: H01L23/12 ,  H01L23/31

CPC classification number: H01L23/3114 ,  H01L23/3171 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05571 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005

Abstract: A low elastic modulus layer (20) having an electrode arranging area that is formed by cutting the layer (20) for arranging element electrodes is provided on the main surface of a semiconductor substrate (10). Lands (32) which function as external electrodes are provided on the layer (20), and pads (30) on the element electrodes, lands (32), and metallic wirings (31) which connect the pads (30) and lands (32) to each other are integrated to constitute a metallic wiring pattern (33). Solder resist films (50) through which part of the lands (32) are opened are formed and metallic balls (40) are put on the lands (32) in the openings of the film (50). The layer (20) is constituted so that it absorbs stresses, such as the thermal stress generated when a semiconductor device is heated or cooled, and thus prevents the disconnection of the wiring (31).

公开(公告)号：EP1653511A2

公开(公告)日：2006-05-03

申请号：EP06002382.7

申请日：1998-05-28

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Shimoishizaka, Nozomi ,  Sahara, Ryuichi ,  Nakamura, Yoshifumi ,  Kumakawa, Takahiro ,  Murakami, Shinji ,  Harada, Yutaka

IPC: H01L23/485 ,  H01L23/31

CPC classification number: H01L23/3114 ,  H01L23/3171 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05571 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005

Abstract: A low elasticity layer (20) having an opening in an electrode arranging area where element electrodes are disposed is provided on a main surface of a semiconductor substrate (10). On the low elasticity layer (20), lands (32) serving as external electrodes are disposed, and pads (30) on the element electrodes, the lands (32) and metal wires (31) for connecting them are integrally formed as a metal wiring pattern (33). A solder resist film (50) having an opening for exposing a part of each land (32) is formed, and a metal ball (40) is provided on the land (32) in the opening. The low elasticity layer (20) absorbs thermal stress and the like caused in heating or cooling the semiconductor device, so as to prevent disconnection of the metal wires (31).

Abstract translation: 在半导体衬底（10）的主表面上设置有在电极配置区域中设置有元件电极的开口的低弹性层（20）。 在低弹性层（20）上设置用作外部电极的焊盘（32），并且元件电极上的焊盘（30），用于连接的焊盘（32）和金属丝（31）一体地形成为金属 布线图案（33）。 形成具有用于暴露每个焊盘（32）的一部分的开口的阻焊膜（50），并且在开口中的焊盘（32）上设置金属球（40）。 低弹性层（20）吸收在加热或冷却半导体器件时引起的热应力等，以防止金属线（31）的断开。