公开(公告)号：EP3111333A1

公开(公告)日：2017-01-04

申请号：EP14884199.2

申请日：2014-02-27

申请人： Empire Technology Development LLC

发明人： SOLIHIN, Yan

IPC分类号： G06F13/14

CPC分类号： G06F9/5033 ,  G06F9/4881 ,  G06F9/5027 ,  G06F11/34 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0875 ,  G06F2201/885 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/62

摘要： Technologies are generally described for methods and systems to assign threads in a multi-core processor. In an example, a method to assign threads in a multi-core processor may include determining data relating to memory controllers fetching data in response to cache misses experienced by a first core and a second core. Threads may be assigned to cores based on the number of cache misses processed by respective memory controllers. Methods may further include determining that a thread is latency-bound or bandwidth-bound. Threads may be assigned to cores based on the determination of the thread as latency-bound or bandwidth-bound. In response to the assignment of the threads to the cores, data for the thread may be stored in the assigned cores.

摘要翻译： 一般来说，为在多核处理器中分配线程的方法和系统描述技术。 在一个示例中，在多核处理器中分配线程的方法可以包括确定与存储器控制器有关的数据，以响应于由第一核心和第二核心经历的高速缓存未命中而获取数据。 可以根据各个存储器控制器处理的高速缓存未命中的数量将线程分配给内核。 方法还可以包括确定线程是等待时间限制的或带宽​​限制的。 线程可以根据线程的确定作为延迟限制或带宽限制分配给内核。 响应于将线程分配给内核，线程的数据可以存储在分配的内核中。