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    Process for fabricating an integrated circuit by a repetition of exposure of a semiconductor pattern
    1.
    发明公开
    Process for fabricating an integrated circuit by a repetition of exposure of a semiconductor pattern 失效
    从半导体制造图案由Wiederholbelichtung集成电路的方法。

    公开(公告)号：EP0485303A2

    公开(公告)日：1992-05-13

    申请号：EP91403020.0

    申请日：1991-11-08

    申请人： FUJITSU LIMITED

    发明人： Ema, Taiji ,  Shirai, Hisatsugu ,  Kobayashi, Katsuyoshi ,  Taguchi, Masao

    IPC分类号： G03F7/20 ,  H01L21/027 ,  H01L21/82

    CPC分类号： H01L28/87 ,  H01L21/0274 ,  H01L21/76802 ,  Y10S438/946

    摘要： A method for fabricating a semiconductor device comprises the steps of defining a plurality of regions (A) on a substrate (2), exposing a first pattern (WL, BL) that extends over a plurality of such regions such that the first pattern is exposed on the plurality of regions simultaneously, and exposing a plurality of second patterns (21, 30) that are identical in size and shape and isolated from each other, consecutively for each of the plurality of regions.

    摘要翻译： 一种用于制造半导体器件的方法包括在一个基片（2）露出第一图案（WL，BL）的限定区域（A）的多元并延伸过检查搜索区域的多个步骤并与第一图案被暴露 上同时区域的多个，并且露出的第二图案的多个（21，30）做在尺寸和形状相同，并从分离海誓山盟，连续地对每个区域的多个。