公开(公告)号：EP4432804A1

公开(公告)日：2024-09-18

申请号：EP23211159.1

申请日：2023-11-21

申请人： Samsung Electronics Co., Ltd.

发明人： LEE, Ahreum ,  YANG, Woosung ,  GU, Jimo ,  SUNG, Sukkang

IPC分类号： H10B41/10 ,  H10B41/27 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/50

CPC分类号： H10B41/10 ,  H10B41/27 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/50 ,  H01L28/40 ,  H01L28/87

摘要： Disclosed are semiconductor devices which may include a substrate having first and second regions, a stack structure including electrode patterns and dielectric patterns, channels vertically penetrating the stack structure on the first region, a planarized dielectric layer covering the stack structure, and wiring patterns on the planarized dielectric layer. The dielectric pattern includes a first dielectric pattern on the first region, and a second dielectric pattern on the second region. The second dielectric pattern includes a first sub-dielectric pattern and a second sub-dielectric pattern. A dielectric constant of the first sub-dielectric patterns is greater than that of the first dielectric patterns and that of the second sub-dielectric patterns.

公开(公告)号：EP4404254A2

公开(公告)日：2024-07-24

申请号：EP24172898.9

申请日：2019-04-10

申请人： Semtech Corporation

发明人： AINSWORTH, Christopher David

IPC分类号： H01L23/49

CPC分类号： H01L23/5223 ,  H01L25/167 ,  H01L23/045 ,  H01L23/49 ,  H01L2224/4825720130101 ,  H01L2224/0555420130101 ,  H01L28/87 ,  H01L28/88 ,  H01L2224/7326520130101

摘要： A semiconductor device comprises a semiconductor die and an integrated capacitor formed over the semiconductor die. The integrated capacitor is configured to receive a high voltage signal. A transimpedance amplifier is formed in the semiconductor die. An avalanche photodiode is disposed over or adjacent to the semiconductor die. The integrated capacitor is coupled between the avalanche photodiode and a ground node. A resistor is coupled between a high voltage input and the avalanche photodiode. The resistor is an integrated passive device (IPD) formed over the semiconductor die. A first terminal of the integrated capacitor is coupled to a ground voltage node. A second terminal of the integrated capacitor is coupled to a voltage greater than 20 volts. The integrated capacitor comprises a plurality of interdigitated fingers in one embodiment. In another embodiment, the integrated capacitor comprises a plurality of vertically aligned plates.

公开(公告)号：EP1766670A2

公开(公告)日：2007-03-28

申请号：EP05751777.3

申请日：2005-05-23

申请人： International Business Machines Corporation

发明人： STAMPER, Anthony, K.

IPC分类号： H01L21/311

CPC分类号： H01L21/7682 ,  H01L21/31116 ,  H01L21/76807 ,  H01L28/87

摘要： A method of forming a semiconductor device, and the device so formed. Depositing alternating layers of a first dielectric material (12a-f) and a second dielectric material (14a-f), wherein the first and second dielectric materials are selectively etchable at different rates. Forming a first feature (22, 24) within the alternating layers of dielectric material. Selectively etching the alternating layers of dielectric material to remove at least a portion (26) of the first dielectric material in each layer having the first dielectric material and leaving the second dielectric material as essentially unetched.

公开(公告)号：EP1351315A3

公开(公告)日：2005-08-17

申请号：EP03100542.4

申请日：2003-03-05

申请人： Memscap

发明人： Girardie, Lionel

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L28/87 ,  C23C16/40 ,  H01L21/28167 ,  H01L21/31604 ,  H01L29/511

摘要： Micro-composant électronique réalisé à partir d'un substrat, et intégrant une structure capacitive réalisée au-dessus d'un niveau de métallisation (3) présent dans le substrat (2), ladite structure capacitive comportant deux électrodes (4,7), caractérisé en ce que: la première électrode (4) comporte une pluralité de lamelles métalliques (14,24,34) empilées les unes au-dessus des autres, et séparées les unes des autres par des tronçons (18,28) de moindre largeur réalisés à partir du même métal, la seconde électrode (7) recouvre la première électrode (4) en comportant une pluralité de lamelles (31,32) intercalées entre les lamelles (14,24,34) de la première électrode (4).

公开(公告)号：EP0813752B1

公开(公告)日：2002-05-02

申请号：EP96901680.7

申请日：1996-02-14

申请人： Nortel Networks Limited

发明人： NG, Anthony, C., C. ,  SARAN, Mukul

IPC分类号： H01L29/92

CPC分类号： H01L23/5223 ,  H01L28/87 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP0601868A1

公开(公告)日：1994-06-15

申请号：EP93309941.8

申请日：1993-12-10

申请人： Samsung Electronics Co., Ltd.

发明人： Choi, Young-jae ,  Chung, Tae-young ,  Park, Jong-woo ,  Kim, Young-pil

IPC分类号： H01L21/82 ,  H01L27/108

CPC分类号： H01L28/86 ,  H01L21/26533 ,  H01L28/87 ,  H01L28/88

摘要： In a manufacturing method for a semiconductor memory device, wherein a capacitor having a double fin-shaped structure is provided, a storage electrode is formed by applying a thick planar material (31) which is capable of being wet-etched, between the double fins consisting of conductive layers (30,34). Accordingly, the problem of a photolithography process caused by poor step difference of a conventional fin structure can be solved. By removing the wet-etchable material (31) before pattern-etching the first conductive layer (30) the storage electrode surface is less likely to be damaged as compared to a RIE step. Further, the storage electrode may be formed by using a thin high temperature oxide film (41) whose etching rate is great. Thus, the cell's topography may be improved and damage to the storage electrode decreased.

摘要翻译： 在具有双翅片状结构的电容器的半导体存储器件的制造方法中，通过在双层翅片之间施加能够被湿蚀刻的厚的平坦材料（31）而形成存储电极， 由导电层（30,34）组成。 因此，可以解决由常规翅片结构的差差产生的光刻工艺的问题。 在图案蚀刻第一导电层（30）之前，通过去除湿蚀刻材料（31），与RIE步骤相比，存储电极表面不太可能被损坏。 此外，可以通过使用蚀刻速率大的薄型高温氧化物膜（41）来形成存储电极。 因此，可以改善电池的形貌并减小对存储电极的损坏。

公开(公告)号：EP0295709A3

公开(公告)日：1990-12-05

申请号：EP88109701.8

申请日：1988-06-16

申请人： FUJITSU LIMITED

发明人： Taguchi, Maso ,  Ema, Taiji

IPC分类号： H01L27/10 ,  H01L21/82

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/40 ,  H01L28/87

摘要： A dynamic random access memory device includes a storage capacitor (C) having a plurality of stacked conductive films (26a₁, 26a₂,..., 26a n ) which form a storage electrode (26a). A gap is formed between elevationally adjacent conductive films so as to surround the storage electrode. A gap (24₁) is formed between an insulating film (15) which covers a gate electrode (WL1) for insulation and a lowermost film (26a₁) of the storage electrode. Connection between the adjacent films is established so that an uppermost film (36₂) elevationally extends so as to make contact with a drain region (13). Also, connection can be established so that an upper film (46₂) is mounted directly on an lower film (46₁). An end portion of the film is thicker than the other portion thereof. The stacked film structure may be produced by alternatively forming a film made of a material different from the insulating film covering the gate electrode, and a conductive film.

公开(公告)号：EP4404254A3

公开(公告)日：2024-09-04

申请号：EP24172898.9

申请日：2019-04-10

申请人： Semtech Corporation

发明人： AINSWORTH, Christopher David

IPC分类号： H01L25/16 ,  H01L23/522 ,  H01L23/045 ,  H01L23/49

CPC分类号： H01L23/5223 ,  H01L25/167 ,  H01L23/045 ,  H01L23/49 ,  H01L2224/4825720130101 ,  H01L2224/0555420130101 ,  H01L28/87 ,  H01L28/88 ,  H01L2224/7326520130101

摘要： A semiconductor device comprises a semiconductor die and an integrated capacitor formed over the semiconductor die. The integrated capacitor is configured to receive a high voltage signal. A transimpedance amplifier is formed in the semiconductor die. An avalanche photodiode is disposed over or adjacent to the semiconductor die. The integrated capacitor is coupled between the avalanche photodiode and a ground node. A resistor is coupled between a high voltage input and the avalanche photodiode. The resistor is an integrated passive device (IPD) formed over the semiconductor die. A first terminal of the integrated capacitor is coupled to a ground voltage node. A second terminal of the integrated capacitor is coupled to a voltage greater than 20 volts. The integrated capacitor comprises a plurality of interdigitated fingers in one embodiment. In another embodiment, the integrated capacitor comprises a plurality of vertically aligned plates.

公开(公告)号：EP2338163B1

公开(公告)日：2017-01-18

申请号：EP09785638.9

申请日：2009-09-14

申请人： Qualcomm Technologies International, Ltd.

发明人： HERBERHOLZ, Rainer

IPC分类号： H01L27/08 ,  H01L23/522 ,  H01L49/02 ,  H01L27/02

CPC分类号： H01L28/91 ,  H01L23/5223 ,  H01L27/0207 ,  H01L27/0805 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

公开(公告)号：EP3050078A1

公开(公告)日：2016-08-03

申请号：EP13894789.0

申请日：2013-09-25

申请人： Intel Corporation

发明人： BASKARAN, Rajashree ,  JUN, Kimin ,  MORROW, Patrick

IPC分类号： H01L21/20

CPC分类号： H01L27/10832 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/10861 ,  H01L27/10867 ,  H01L27/1087 ,  H01L28/20 ,  H01L28/87 ,  H01L28/91 ,  H01L29/945

摘要： Methods of forming passive elements under a device layer are described. Those methods and structures may include forming at least one passive structure, such as a capacitor and a resistor structure, in a substrate, wherein the passive structures are vertically disposed within the substrate. An insulator layer is formed on a top surface of the passive structure, a device layer is formed on the insulator layer, and a contact is formed to couple a device disposed in the device layer to the at least one passive structure.

摘要翻译： 描述了在器件层下形成无源元件的方法。 这些方法和结构可以包括在衬底中形成至少一个无源结构，例如电容器和电阻器结构，其中被动结构垂直地设置在衬底内。 在无源结构的顶表面上形成绝缘体层，在绝缘体层上形成器件层，并且形成接触以将设置在器件层中的器件耦合到至少一个被动结构。