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公开(公告)号:EP1603136A2
公开(公告)日:2005-12-07
申请号:EP05017186.7
申请日:1998-06-03
申请人: FUJITSU LIMITED
发明人: Fujioka, Shinya , Taguchi, Masao , Fujieda, Waichirou , Sato, Yasuharu , Susuki, Takaaki , Aikawa, Tadao , Nagasawa, Takayuki
IPC分类号: G11C11/4091
CPC分类号: G11C7/06 , G11C7/1039 , G11C7/1072 , G11C7/12 , G11C8/00 , G11C8/08 , G11C8/10 , G11C11/4085 , G11C11/4091 , G11C11/4094 , G11C2207/005 , G11C2207/065
摘要: A semiconductor memory device comprising: a memory cell array block (150) including a plurality of sub memory cell array blocks (162); a sense amplifier column associated with said memory cell array block, the sense amplifier column including a plurality of sense amplifier blocks (164), each associated with corresponding sub memory cell array block; a column decoder receiving a column address to output a column block select signal; and a sense amplifier driving signal generating circuit for driving specified sense amplifier block among the plurality of sense amplifier blocks (164) in response to said column block select signal.
摘要翻译: 一种半导体存储器件,包括:包括多个子存储单元阵列块(162)的存储单元阵列块(150); 与所述存储单元阵列块相关联的读出放大器列,所述读出放大器列包括多个读出放大器块(164),每个读出放大器列与对应的子存储单元阵列块相关联; 接收列地址以输出列块选择信号的列解码器; 以及用于响应于所述列块选择信号而驱动多个读出放大器块(164)中的指定读出放大器块的读出放大器驱动信号发生电路。
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公开(公告)号:EP1603136A3
公开(公告)日:2007-06-06
申请号:EP05017186.7
申请日:1998-06-03
申请人: FUJITSU LIMITED
发明人: Fujioka, Shinya , Taguchi, Masao , Fujieda, Waichirou , Sato, Yasuharu , Susuki, Takaaki , Aikawa, Tadao , Nagasawa, Takayuki
IPC分类号: G11C11/4091
CPC分类号: G11C7/06 , G11C7/1039 , G11C7/1072 , G11C7/12 , G11C8/00 , G11C8/08 , G11C8/10 , G11C11/4085 , G11C11/4091 , G11C11/4094 , G11C2207/005 , G11C2207/065
摘要: A semiconductor memory device comprising: a memory cell array block (150) including a plurality of sub memory cell array blocks (162); a sense amplifier column associated with said memory cell array block, the sense amplifier column including a plurality of sense amplifier blocks (164), each associated with corresponding sub memory cell array block; a column decoder receiving a column address to output a column block select signal; and a sense amplifier driving signal generating circuit for driving specified sense amplifier block among the plurality of sense amplifier blocks (164) in response to said column block select signal.
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