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223 条记录 (耗时 0.017 秒)

    READ/WRITE SWITCHING CIRCUIT AND MEMORY
    2.
    发明公开
    READ/WRITE SWITCHING CIRCUIT AND MEMORY 审中-公开

    公开(公告)号：EP4435788A2

    公开(公告)日：2024-09-25

    申请号：EP24193554.3

    申请日：2021-03-01

    申请人： Changxin Memory Technologies, Inc.

    发明人： SHANG, Weibing

    IPC分类号： G11C13/00

    CPC分类号： G11C11/4091 ,  G11C11/409 ,  G11C11/419 ,  G11C2013/004220130101 ,  G11C7/222 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1096

    摘要： Some embodiments of the present application relate to the field of semiconductor technologies, and disclose a read/write switching circuit and a memory. The read/write switching circuit includes: a first data line connected to a bit line through a column select module, a first complementary data line connected to a complementary bit line through the column select module, a second data line and a second complementary data line, and further includes: a read/write switching module configured to transmit data between the first data line and the second data line and transmit data between the first complementary data line and the second complementary data line during read and write operations in response to read and write control signals; and an amplification module connected between the first data line and the first complementary data line and configured to amplify data of the first data line and data of the first complementary data line.

    LATCHED COMPARATOR CIRCUIT
    4.
    发明公开
    LATCHED COMPARATOR CIRCUIT 审中-公开
    锁存比较器电路

    公开(公告)号：EP3314763A1

    公开(公告)日：2018-05-02

    申请号：EP16815019.1

    申请日：2016-06-02

    申请人： Intel Corporation

    发明人： AW, Chee Hong

    IPC分类号： H03K3/288 ,  H03K3/356

    CPC分类号： H03K3/356113 ,  G11C7/065 ,  G11C7/1084 ,  G11C7/1087 ,  H03K3/037 ,  H03K3/356139 ,  H03K3/356191 ,  H03K5/249

    摘要： Some embodiments include apparatuses having input nodes to receive input signals, output nodes to provide output signals, a first stage including a first pair of input transistors, the first pair of transistors including gates coupled to the input nodes, a second stage including a second pair of input transistors, the second pair of transistors including gates coupled to the input nodes, and a third stage including inverters coupled to the output nodes. The inverters are coupled to the first and second stages at the same nodes to switch the output signals between different voltages based on the input signals.

    METHOD AND SYSTEM FOR MAXIMIZING DRAM MEMORY BANDWIDTH
    8.
    发明授权
    METHOD AND SYSTEM FOR MAXIMIZING DRAM MEMORY BANDWIDTH 有权
    方法和设备最大化DRAM内存带宽

    公开(公告)号：EP1485919B1

    公开(公告)日：2012-04-25

    申请号：EP03714158.7

    申请日：2003-03-13

    申请人： Intel Corporation

    发明人： KURUPATI, Sreenath

    IPC分类号： G11C7/10 ,  G11C11/4093 ,  G11C11/408

    CPC分类号： G11C7/1087 ,  G11C7/1078 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4093

    摘要： A method and system for maximizing DRAM memory bandwidth is provided. The system includes a plurality of buffers to store a plurality of data units, a selector coupled to the buffers to select the buffer to which a data unit is to be stored, and logic coupled to the buffers to schedule an access of one of a corresponding number of memory banks based on the buffer in which the data unit is stored. The system receives a data unit, computes an index based on at least a portion of the data unit, selects a buffer in which to store the data unit based on the index, stores the data unit in the selected buffer, schedules a memory bank access based on the index, reads the data unit from the selected buffer, and accesses the memory bank.

    Apparatus for data recovery in a synchronous chip-to-chip system
    9.
    发明公开
    Apparatus for data recovery in a synchronous chip-to-chip system 有权
    一种用于在同步芯片到芯片上系统的数据恢复

    公开(公告)号：EP2197143A2

    公开(公告)日：2010-06-16

    申请号：EP10156597.6

    申请日：2002-06-18

    申请人： Rambus Inc.

    发明人： Best, Scott C. ,  Warmke, Richard E. ,  Roberts, David B.

    IPC分类号： H04L7/033 ,  H03L7/07 ,  H03L7/081 ,  G06F1/10

    CPC分类号： G11C11/4076 ,  G06F1/10 ,  G11C7/04 ,  G11C7/10 ,  G11C7/1087 ,  G11C7/222 ,  G11C11/4091 ,  G11C2207/107 ,  H03L7/07 ,  H03L7/0814 ,  H04L7/0337

    摘要： An apparatus (50) that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal (DQS) to align a data-sampling signal (DSS) for sampling data signal (DQ1 DQN) that was sent along with the timing reference signal (DQS). The data-sampling signal (DDS) may be provided by adjustably delaying a clock signal (CLK) according to the information acquired from the strobe signal (DQS). The data-sampling signal (DSS) may also have in improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal (DQS) may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.