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5 条记录 (耗时 0.008 秒)

    Gate circuit device
    1.
    发明公开
    Gate circuit device 失效
    门电路设备

    公开(公告)号：EP0151875A3

    公开(公告)日：1987-07-15

    申请号：EP84308520

    申请日：1984-12-07

    申请人： FUJITSU LIMITED

    发明人： Suzuki, Hirokazu c/o Fujitsu Ltd. ,  Akiyama, Takehiro c/o Fujitsu Ltd. ,  Morita, Teruo c/o Fujitsu Ltd. ,  Masunaga, Hikotaro ,  Takeda, Hirofumi

    IPC分类号： H03K05/13

    CPC分类号： H03K5/13 ,  G01R31/3191 ,  H03K19/086

    摘要： A gate circuit device, for example for an integrated circuit tester (10, 20), for variably setting signal propagation delay time (Tpd), for example to control timings of various output signals delivered from the IC tester to an integrated circuit (11) to be tested to predetermined values, comprises a gate circuit having a pair of emitter coupled transistors (01, Q2) and a constant current source transistor (Q3) connected to the emitter side of the pair of transistors (Q1, Q2) and a terminal for applying a predetermined level of voltage (VC, Vs) to the base of the constant current source transistor (Q3) to control constant current (Figure 1). As an alternative (Figure 6) to such voltage control of signal propagation delay time, a current adjustment circuit (CONT) may be utilized to generate current in a constant current source transistor (e.g. Q35) in response to a control current (I CNT )· Thus, the gate circuot device controls signal propagation delay time by regulating either voltage or current in response to control current.

    Emitter coupled logic circuit
    2.
    发明公开
    Emitter coupled logic circuit 失效
    一个发射极耦合逻辑电路。

    公开(公告)号：EP0098074A1

    公开(公告)日：1984-01-11

    申请号：EP83303428.3

    申请日：1983-06-14

    申请人： FUJITSU LIMITED

    发明人： Takeda, Hirofumi ,  Suzuki, Hirokazu

    IPC分类号： H03K19/003 ,  H03K19/086

    CPC分类号： H03K19/086

    摘要： An emitter coupled logic circuit (10) comprises a differential transistor pair (11A, 11A) and a set transistor (12), which are all emitter coupled. The high voltage logic level (V SH ) of a set input signal (S) to be applied, as a control input signal, to the set transistor (12) is higher than the high voltage logic level (V AH ) of the complementary logic input signal (a) to be applied, as a control input signal, to the differential transistor pair (11A, 11A). Simultaneously, the low voltage logic level (V SL ) of the set input signal (S) is lower than the low voltage logic level (V AL ) of the complementary logic input signal (a). These voltage differentials may be achieved by means of level converter circuits (41,42).

    Gate circuit device
    5.
    发明公开
    Gate circuit device 失效
    门控电路。

    公开(公告)号：EP0151875A2

    公开(公告)日：1985-08-21

    申请号：EP84308520.0

    申请日：1984-12-07

    申请人： FUJITSU LIMITED

    发明人： Suzuki, Hirokazu c/o Fujitsu Ltd. ,  Akiyama, Takehiro c/o Fujitsu Ltd. ,  Morita, Teruo c/o Fujitsu Ltd. ,  Takeda, Hirofumi ,  Masunaga, Hikotaro

    IPC分类号： H03K5/13

    CPC分类号： H03K5/13 ,  G01R31/3191 ,  H03K19/086

    摘要： A gate circuit device, for example for an integrated circuit tester (10, 20), for variably setting signal propagation delay time (Tpd), for example to control timings of various output signals delivered from the IC tester to an integrated circuit (11) to be tested to predetermined values, comprises a gate circuit having a pair of emitter coupled transistors (01, Q2) and a constant current source transistor (Q3) connected to the emitter side of the pair of transistors (Q1, Q2) and a terminal for applying a predetermined level of voltage (VC, Vs) to the base of the constant current source transistor (Q3) to control constant current (Figure 1). As an alternative (Figure 6) to such voltage control of signal propagation delay time, a current adjustment circuit (CONT) may be utilized to generate current in a constant current source transistor (e.g. Q35) in response to a control current (I CNT )· Thus, the gate circuot device controls signal propagation delay time by regulating either voltage or current in response to control current.