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    Semiconductor logic circuit
    1.
    发明公开
    Semiconductor logic circuit 失效
    Halbleiter-Logikschaltung。

    公开(公告)号：EP0270296A2

    公开(公告)日：1988-06-08

    申请号：EP87310378.2

    申请日：1987-11-25

    申请人： FUJITSU LIMITED ,  FUJITSU VLSI LIMITED

    发明人： Suzuki, Hirokazu ,  Tahara, Akinori ,  Saito, Shinji

    IPC分类号： H03K19/013

    CPC分类号： H03K5/02 ,  H03K19/212

    摘要： A semiconductor logic circuit comprises a clock driver circuit (21) and a clocked circuit (22) which carries out a clocked operation responsive to an output of the clock driver circuit, where an output logic amplitude (L 1 ) of the clock driver circuit is set to a value which is greater than an internal logic amplitude (L 2 ) of the clocked circuit and is less than or equal to four times the internal logic amplitude of the clocked circuit.

    摘要翻译： 半导体逻辑电路包括响应于时钟驱动电路（21）的输出执行时钟控制的时钟驱动电路（21）和时钟电路（22），其中时钟驱动器的输出逻辑幅度（L1） 电路（21）被设置为大于时钟控制电路（22）的内部逻辑振幅（L2）的值，小于或等于时钟电路（22）的内部逻辑振幅（L2）的四倍， 。

    Semiconductor logic circuit
    2.
    发明公开
    Semiconductor logic circuit 失效
    半导体逻辑电路

    公开(公告)号：EP0270296A3

    公开(公告)日：1990-02-07

    申请号：EP87310378.2

    申请日：1987-11-25

    申请人： FUJITSU LIMITED ,  FUJITSU VLSI LIMITED

    发明人： Suzuki, Hirokazu ,  Tahara, Akinori ,  Saito, Shinji

    IPC分类号： H03K19/013

    CPC分类号： H03K5/02 ,  H03K19/212

    摘要： A semiconductor logic circuit comprises a clock driver circuit (21) and a clocked circuit (22) which carries out a clocked operation responsive to an output of the clock driver circuit, where an output logic amplitude (L 1 ) of the clock driver circuit is set to a value which is greater than an internal logic amplitude (L 2 ) of the clocked circuit and is less than or equal to four times the internal logic amplitude of the clocked circuit.

    摘要翻译： 半导体逻辑电路包括时钟驱动器电路（21）和时钟控制电路（22），其响应于时钟驱动器电路的输出执行时钟控制操作，其中时钟驱动器电路的输出逻辑振幅（L1）被设置 变为大于时钟电路的内部逻辑振幅（L2）的值并且小于或等于时钟电路的内部逻辑振幅的四倍。

    Semiconductor device having input protection circuit
    5.
    发明公开
    Semiconductor device having input protection circuit 失效
    Halbleiteranordnung mit Eingangsschutzschaltung。

    公开(公告)号：EP0130737A1

    公开(公告)日：1985-01-09

    申请号：EP84304170.8

    申请日：1984-06-20

    申请人： FUJITSU LIMITED

    发明人： Tahara, Akinori ,  Enomoto, Hiromu ,  Yasuda, Yasushi

    IPC分类号： H01L27/02 ,  H03K19/00

    CPC分类号： H01L27/0248 ,  H03K19/00307

    摘要： This concerns a semiconductor device such as a TTL-type integrated circuit device which has an input protection circuit for each inner circuit, e.g., each TTL logic gate. The input protection circuit is formed on a semiconductor substrate (2) having a first conductivity type, and comprises: a first impurity region (1) having a second conductivity type connected to an external terminal (3a) and having an island-shape formed on the semiconductor substrate and surrounded by an isolation region (2a) having the first conductivity type; a clamp diode (D1) comprising an electrode layer (4) contacting the first impurity region (1); and a PN junction type protection diode (D3) comprising a second impurity region (9) having the first conductivity type which crosses the first impurity region (1) between the clamp diode and a portion (3) of the first impurity region (1) connected to the external terminal, and which reaches the isolation region (23a). The reverse withstand voltage of the PN junction type protection diode (D3, 9-1) is smaller than that of the clamp diode (01,4-1) thereby avoiding permanent destruction of the clamp diode.

    摘要翻译： 这涉及诸如TTL型集成电路器件的半导体器件，其具有用于每个内部电路的输入保护电路，例如每个TTL逻辑门。 输入保护电路形成在具有第一导电类型的半导体衬底（2）上，并且包括：具有第二导电类型的第一杂质区（1），其连接到外部端子（3a）并形成为岛状 半导体衬底并被具有第一导电类型的隔离区域（2a）包围; 钳位二极管（D1），包括与第一杂质区（1）接触的电极层（4）; 以及PN结型保护二极管（D3），其包括具有第一导电类型的第二杂质区域（9），该第二杂质区域穿过钳位二极管与第一杂质区域（1）的部分（3）之间的第一杂质区域（1） 连接到外部端子，并且到达隔离区域（23a）。 PN结型保护二极管（D3,9-1）的反向耐压小于钳位二极管（D1，4-1）的反向耐受电压，从而避免了钳位二极管的永久性破坏。

    Logic circuit employing bipolar-transistors and stable upon starting-up of power supply therefor
    6.
    发明公开
    Logic circuit employing bipolar-transistors and stable upon starting-up of power supply therefor 失效
    使用双极晶体管的逻辑电路和稳定的电源启动

    公开(公告)号：EP0253555A3

    公开(公告)日：1989-07-05

    申请号：EP87305986.9

    申请日：1987-07-07

    申请人： FUJITSU LIMITED

    发明人： Enomoto, Hiromu ,  Yasuda, Yasushi ,  Kumagai, Masao ,  Tahara, Akinori

    IPC分类号： H03K19/003 ,  H03K17/22

    CPC分类号： H03K19/00353 ,  H03K17/22 ,  H03K19/088 ,  H03K2017/226

    摘要： A logic circuit employing bipolar-transistors and including a level-shift circuit unit, in addition to a normal bipolar logic circuit, for improving a stability of the circuit upon start-up of a power supply. The logic circuit includes: an input circuit (l) receiving at least one input signal (SIN) and connected to a terminal of a power supply; a first internal circuit including a first bipolar transistor (T3), a base of which is connected to an output of the input circuit, and a level-shift circuit (D2) connected between a terminal of the first bipolar transistor and another terminal of the power supply; a level-shift circuit unit (3) connected between the terminal of the power supply and another terminal of the first bipolar transistor; a second internal circuit including a second bipolar transistor (T4) a base of which is connected to a commonly-connected point of the level-shift circuit unit and another terminal of the first bipolar transistor; and an output circuit means including a third bipolar transistor (T5) a base of which is connected to an output terminal of the second bipolar transistor, a terminal of which is connected to another terminal of the power supply and another terminal of which is provided for connection to a load circuit. A forward voltage of the level-shift circuit unit, the second internal circuit and the output circuit is higher than a forward voltage of the first internal circuit. The first to third bipolar transistors have the same operational polarities.

    摘要翻译： 采用双极晶体管并且包括电平移位电路单元的逻辑电路，除了正常的双极逻辑电路之外，用于在电源启动时改善电路的稳定性。 逻辑电路包括：输入电路（1），其接收至少一个输入信号（SIN）并连接到电源的端子; 包括第一双极晶体管（T3）的第一内部电路，其基极连接到所述输入电路的输出;以及电平移位电路（D2），连接在所述第一双极晶体管的端子和所述第二双极晶体管的另一端子之间 电源; 电平移位电路单元（3），连接在电源的端子与第一双极晶体管的另一端子之间; 第二内部电路，包括第二双极晶体管（T4），第二双极晶体管（T4）的基极连接到电平移位电路单元的共同连接点和第一双极晶体管的另一端子; 以及包括第三双极晶体管（T5）的输出电路装置，其基极连接到第二双极晶体管的输出端子，其端子连接到电源的另一个端子，另一个端子用于 连接到负载电路。 电平移位电路单元，第二内部电路和输出电路的正向电压高于第一内部电路的正向电压。 第一至第三双极晶体管具有相同的工作极性。

    A logic circuit
    7.
    发明公开
    A logic circuit 失效
    逻辑电路

    公开(公告)号：EP0173148A3

    公开(公告)日：1987-09-30

    申请号：EP85110031

    申请日：1985-08-09

    申请人： FUJITSU LIMITED

    发明人： Enomoto, Hiromu ,  Yasuda, Yasushi ,  Kumagai, Masao ,  Tahara, Akinori

    IPC分类号： H03K19/003

    CPC分类号： H03K19/00307 ,  H03K17/0826

    摘要： The present invention relates to a logic circuit which reduces occurrence of breakdown of a pull-down transistor (T 3 ) and a pull-up transistor (T 4 ; T a ) in the output stage when a high voltage is applied to the power supply line and ensures high voltage resistance. The logic circuit of the present invention controls the pull-up transistor (T 4 ; T,) provided between a first power supply (V cc ) and an output terminal (OUT) for ON and OFF with a collector voltage of a phase splitter transistor (T 2 ) and controls the pull-down transistor (T 3 ) provided between the second power supply (GND) and the output terminal (OUT) with an emitter voltage. Breakdown of said pull-down and pull-up transistors (T 3 ; T 4 ; T.) can be reduced and a high voltage resistance is ensured by providing a protection circuit (P) which discharges the base of pull-down transistor (T 3 ) and turns OFF said pull-down transistor (T 3 ) by detecting a voltage difference between the first power supply (V cc ) and the second power supply (GND) when it exceeds the specified value.

    A logic circuit
    8.
    发明公开
    A logic circuit 失效
    一个逻辑电路

    公开(公告)号：EP0173148A2

    公开(公告)日：1986-03-05

    申请号：EP85110031.3

    申请日：1985-08-09

    申请人： FUJITSU LIMITED

    发明人： Enomoto, Hiromu ,  Yasuda, Yasushi ,  Kumagai, Masao ,  Tahara, Akinori

    IPC分类号： H03K19/003

    CPC分类号： H03K19/00307 ,  H03K17/0826

    摘要： The present invention relates to a logic circuit which reduces occurrence of breakdown of a pull-down transistor (T 3 ) and a pull-up transistor (T 4 ; T a ) in the output stage when a high voltage is applied to the power supply line and ensures high voltage resistance. The logic circuit of the present invention controls the pull-up transistor (T 4 ; T,) provided between a first power supply (V cc ) and an output terminal (OUT) for ON and OFF with a collector voltage of a phase splitter transistor (T 2 ) and controls the pull-down transistor (T 3 ) provided between the second power supply (GND) and the output terminal (OUT) with an emitter voltage. Breakdown of said pull-down and pull-up transistors (T 3 ; T 4 ; T.) can be reduced and a high voltage resistance is ensured by providing a protection circuit (P) which discharges the base of pull-down transistor (T 3 ) and turns OFF said pull-down transistor (T 3 ) by detecting a voltage difference between the first power supply (V cc ) and the second power supply (GND) when it exceeds the specified value.

    摘要翻译： 本发明涉及一种逻辑电路，其在向电源线施加高电压时减少输出级中的下拉晶体管（T3）和上拉晶体管（T4; Ta）的击穿的发生并且确保 耐高压。 本发明的逻辑电路利用分相器晶体管（T2）的集电极电压控制提供在第一电源（Vcc）和输出端（OUT）之间用于导通和截止的上拉晶体管（T4; T） ），并用发射极电压控制设置在第二电源（GND）和输出端（OUT）之间的下拉晶体管（T3）。 通过提供对下拉晶体管（T3）的基极进行放电的保护电路（P），可以减小所述下拉和上拉晶体管（T3; T4; T）的击穿并且确保高电压电阻;以及 当其超过规定值时，通过检测第一电源（Vcc）和第二电源（GND）之间的电压差来关断所述下拉晶体管（T3）。

    Semiconductor device
    9.
    发明公开
    Semiconductor device 失效
    半导体设备。

    公开(公告)号：EP0090738A2

    公开(公告)日：1983-10-05

    申请号：EP83400644.7

    申请日：1983-03-29

    申请人： FUJITSU LIMITED

    发明人： Enomoto, Hiromu ,  Yasuda, Yasushi ,  Shimauchi, Yoshiki ,  Tahara, Akinori

    IPC分类号： H01L27/02

    CPC分类号： H01L21/74 ,  H01L21/743 ,  H01L27/0248

    摘要： Electrostatical breakage of a semiconductor device comprising an epitaxial layer (106) and a buried layer (104) thereunder connected with an outer signal terminal (114-116) can be prevented by forming an impurity region (118) in the epitaxial layer so as to make a PN junction between the buried layer and the impurity region, the impurity region being connected with a power source or ground.