利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

93 条记录 (耗时 0.012 秒)

    OUTPUT DRIVER CIRCUIT WITH JUMP START FOR CURRENT SINK ON DEMAND
    1.
    发明公开
    OUTPUT DRIVER CIRCUIT WITH JUMP START FOR CURRENT SINK ON DEMAND 审中-公开
    变化无常的START对于购房者相关的电流源输出驱动器

    公开(公告)号：EP0960477A1

    公开(公告)日：1999-12-01

    申请号：EP98944162.0

    申请日：1998-10-05

    申请人： Koninklijke Philips Electronics N.V.

    发明人： ANDERSON, Alma, Stephenson ,  OEHLER, David, William

    IPC分类号： H03K19

    CPC分类号： H03K19/00353 ,  H03K19/001 ,  H03K19/0136

    摘要： An output driver circuit for coupling a logic circuit to load includes an input node, an output node for coupling to the load and a pull down switch which discharges the output node in response to a signal received at the input node. A current sink circuit includes a feeder transistor which provides current to the control terminal of the pull down switch to render the pull down switch conductive when the voltage at the output node exceeds a first threshold value between a logic high and a logic low. The feeder transistor is charged by a first charging path having a first impedance by which it takes a first time period to render the pull down switch conductive, the first impedance providing a low standby current when the voltage at the output node is below about the first value. A jump start circuit having a second current path with a lower impedance than the first current path charges the control terminal of the feeder transistor to said threshold faster than said first path and is disabled when the voltage at the ouput node falls below about the first value, thereby saving power.

    Transistor-transistor logic circuit with internal delay elements
    5.
    发明公开
    Transistor-transistor logic circuit with internal delay elements 失效
    晶体管 - 逻辑电路

    公开(公告)号：EP0266218A3

    公开(公告)日：1989-08-23

    申请号：EP87309629.1

    申请日：1987-10-30

    申请人： FUJITSU LIMITED

    发明人： Hirochi, Katsuji

    IPC分类号： H03K19/088 ,  H03K19/003

    CPC分类号： H03K19/088 ,  H03K19/00353

    摘要： A transistor-transistor logic circuit, i.e., TTL circuit includes at least one input terminal (IN), an output transistor (T10) and elements (1, T11, T12) operatively connected between the input terminal (IN) and the base of the output transistor (T10). The elements include a plurality of delay parts (R15,C1,R16,C2), each having a different signal propagation delay time respectively and feeding base currents (IB1, IB2) to the base of the output transistor (T10) in sequence at a different timing. As a result, a quick change in the output is prevented and thus an overshoot, ringing or noise can be prevented, while realizing an increased driving ability. At the same time, optimum output characteristics can be obtained according to a load to be driven by the TTL circuit.

    A method and apparatus for reducing and maintaining constant overshoot in a high speed driver
    6.
    发明公开
    A method and apparatus for reducing and maintaining constant overshoot in a high speed driver 失效
    方法和电路用于减少和维持在驱动器高速恒定过冲。

    公开(公告)号：EP0286808A2

    公开(公告)日：1988-10-19

    申请号：EP88102733.8

    申请日：1988-02-24

    申请人： International Business Machines Corporation

    发明人： Gruodis, Algirdas Joseph ,  Hoffman, Dale Eugene ,  Puntar, Charles Albert ,  Skooglund, Daniel Edward

    IPC分类号： H03K19/013 ,  H03K19/086 ,  H03K19/003

    CPC分类号： H03K19/01831 ,  H03K19/00353

    摘要： Disclosed is a method and circuit for reducing and maintaining constant overshoot in a high speed driver. The circuit includes a predriver circuit which is driven single endedly and a driver circuit which is differentially driven by the predriver outputs. The predriver and the driver are differen­tial pairs, with commonly controlled individual transistor current sources. A diode has been added in series with each emitter of the differential pairs. Schottky diodes are preferable because of their low capacitance. The diodes increase the input switching voltage (the smallest input voltage swing that will cause the outputs to fully switch) of the differential pair because they must also be switched on and off. The increase results in an increase in effective transition time, which results in smaller overshoots because the circuit is being switched slower. The output amplitude of the driver is set by a voltage which controls the current source currents of the commonly controlled current sources. As the amplitude is decreased the input switching voltage decreases because the current through the devices decreases which results in smaller base-emitter and diode voltages. Due to the commonly controlled current sources, the predriver amplitude decreases as the driver amplitude decreases. The predriver is designed such that its variable output supplies the driver with the proper input switching voltage at any driver amplitude. This keeps the effective input transition time constant which results in constant output overshoot.

    摘要翻译： 公开了一种用于减少和在高速驱动器保持恒定的过冲的方法和电路。 该电路包括预驱动器电路的所有被驱动单端形式和驱动器电路，其全部被差分由预驱动器输出驱动。 预驱动器和驱动器是差分对，与常用控制单独的晶体管的电流源。 二极管已在一系列被添加与差动对每个发射器。 肖特基二极管是由于它们的低电容的优选。 二极管增加输入切换电压（最小输入电压摆动thatwill导致输出到完全切换）的差动对，因为它们必须因此打开和关闭。所述增加导致在有效过渡时间增加了进行切换，这导致 较小的过冲，因为电路正在切换慢。 所述驱动器的输出振幅由它控制的常用控制电流源的电流源电流的电压设定。 作为振幅减小时，输入切换电压减小，因为通过设备跌幅，这导致更小的基极 - 发射极二极管和电压下的电流。 由于通常受控电流源，其幅度减小预驱动器作为驱动振幅减小。 预驱动器被设计检查做它的可变输出提供在任何驱动振幅适当的输入切换电压的驱动程序。 这样可以使有效投入转变的时间常数导致恒定的输出过冲。

    Deglitching network for digital logic circuits
    7.
    发明公开
    Deglitching network for digital logic circuits 失效
    数字逻辑电路的退火网络

    公开(公告)号：EP0201429A3

    公开(公告)日：1988-09-21

    申请号：EP86400982

    申请日：1986-05-07

    申请人： FAIRCHILD SEMICONDUCTOR CORPORATION

    发明人： Luich, Thomas M.

    IPC分类号： H03K19/00 ,  H03K05/00 ,  H03K05/08

    CPC分类号： H03K19/00353 ,  H03K5/08 ,  H03K19/00376

    摘要： A deglitching network for digital logic circuits includes a voltage actuated current source coupled to a linear tracking, constant voltage column clamp circuit. The deglitching network threshold level tracks closely with the predetermined voltage of the column clamp, which also acts as a current sink. When heavy current loads are switched from the column clamp and its voltage falls briefly, the deglitching network is actuated to inject current into the column clamp circuit and restore the preset voltage.

    Transistor-transistor logic circuit with internal delay elements
    8.
    发明公开
    Transistor-transistor logic circuit with internal delay elements 失效
    晶体管 - 晶体管 - Logikschaltung mit internenVerzögerungsgliedern。

    公开(公告)号：EP0266218A2

    公开(公告)日：1988-05-04

    申请号：EP87309629.1

    申请日：1987-10-30

    申请人： FUJITSU LIMITED

    发明人： Hirochi, Katsuji

    IPC分类号： H03K19/088 ,  H03K19/003

    CPC分类号： H03K19/088 ,  H03K19/00353

    摘要： A transistor-transistor logic circuit, i.e., TTL circuit includes at least one input terminal (IN), an output transistor (T10) and elements (1, T11, T12) operatively connected between the input terminal (IN) and the base of the output transistor (T10). The elements include a plurality of delay parts (R15,C1,R16,C2), each having a different signal propagation delay time respectively and feeding base currents (IB1, IB2) to the base of the output transistor (T10) in sequence at a different timing. As a result, a quick change in the output is prevented and thus an overshoot, ringing or noise can be prevented, while realizing an increased driving ability. At the same time, optimum output characteristics can be obtained according to a load to be driven by the TTL circuit.

    摘要翻译： 晶体管晶体管逻辑电路即TTL电路包括至少一个输入端（IN），输出晶体管（T10）和可操作地连接在输入端（IN）和基极之间的元件（1，T11，T12） 输出晶体管（T10）。 这些元件包括分别具有不同的信号传播延迟时间的多个延迟部分（R15，C1，R16，C2），并将基极电流（IB1，IB2）依次馈送到输出晶体管（T10）的基极 不同的时机。 结果，防止输出的快速变化，从而可以在实现增加的驾驶能力的同时防止过冲，振铃或噪音。 同时，可以根据由TTL电路驱动的负载获得最佳的输出特性。

    Integrated logic circuit incorporating a module which generates a control signal that cancels switching noise
    9.
    发明公开
    Integrated logic circuit incorporating a module which generates a control signal that cancels switching noise 失效
    集成逻辑电路，其中包含一个消除了切换噪声的控制信号的模块

    公开(公告)号：EP0186385A3

    公开(公告)日：1988-04-27

    申请号：EP85309026

    申请日：1985-12-12

    申请人： UNISYS CORPORATION

    发明人： Gal, Laszlo Volgyesi

    IPC分类号： H03K19/00 ,  H03K17/16

    CPC分类号： H03K19/00353 ,  H03K17/16

    摘要： A circuit having reduced susceptibility to noise includes a plurality of drivers coupled to a current bus; each driver receives a logic signal on a control terminal and operates to pass a large current when the logic signal is a one and pass a small current when the logic signal is a zero; the current bus has a parasitic inductance which generates a noise signal when the logic signals switch; noise on the current bus is parasitically coupled to the control terminal of each driver; and a plurality of noise reducing modules respectively couple to the control terminal of each driver and a common bus, Each module that receives a switching logic signal generates a control signal on the common bus that is similar in shape and opposite in polarity to the noise signal; and each module that does not receive a switching logic signal couples the control signal from the common bus to the control terminal to which it is connected.

    ECL Gate array
    10.
    发明公开
    ECL Gate array 失效
    ECL门阵列

    公开(公告)号：EP0144218A3

    公开(公告)日：1987-01-28

    申请号：EP84308308

    申请日：1984-11-29

    申请人： FUJITSU LIMITED

    发明人： Kanai, Yasunori ,  Nawata, Kazumasa ,  Shimizu, Mitsuhisa

    IPC分类号： H03K19/177 ,  H03K19/086

    CPC分类号： H03K19/00353 ,  H03K19/086 ,  H03K19/1735

    摘要： An ECL gate array comprising a plurality of basic cells. Each basic cell has a pair of emitter-coupled transistors (Q 1 , Q 2 ), and a load (R o , R 1A , R 1B , R C1 ) connected between the collectors of the transistors and a power supply line (V cc ). In accordance with a circuit design information, the resistance value of the load can be selected for increasing a noise margin of the output logic levels without deteriorating the switching speed.