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    Memory device, memory controller and memory system
    1.
    发明公开
    Memory device, memory controller and memory system 有权
    内存设备，内存控制器和内存系统

    公开(公告)号：EP2061036A1

    公开(公告)日：2009-05-20

    申请号：EP08169914.2

    申请日：2007-07-12

    申请人： Fujitsu Limited

    发明人： Kawakubo, Tomohiro c/o Fujitsu Limited ,  Yamaguchi, Syusaku c/o Fujitsu Limited ,  Ikeda, Hitoshi c/o Fujitsu Limited ,  Uchida, Toshiya c/o Fujitsu Limited ,  Kobayashi, Hiroyuki c/o Fujitsu Limited ,  Kanda, Tatsuya c/o Fujitsu Limited ,  Yamamoto, Yoshinobu c/o Fujitsu Limited ,  Shirakawa, Satoru c/o Fujitsu Limited ,  Miyamoto, Tetsuo c/o Fujitsu Limited ,  Otsuka, Tatsushi c/o Fujitsu Limited ,  Takahashi, Hidenaga c/o Fujitsu Limited ,  Kurita, Masanori c/o Fujitsu Limited ,  Kamata, Shinnosuke c/o Fujitsu Limited ,  Sato, Ayako c/o Fujitsu Limited

    IPC分类号： G11C11/406

    CPC分类号： G11C11/406 ,  G11C7/1027 ,  G11C8/12 ,  G11C11/40618 ,  G11C11/4087

    摘要： Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller (82) has a plurality of banks that respectively have memory cores (92) including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which controls operation of the memory cell arrays within the banks, wherein each of the plurality of banks stores two-dimensionally arrayed data on the basis of a memory mapping of which a memory logical space has a plurality of page areas that are selected by the bank addresses and row addresses, in which the plurality of page areas are arranged in rows and columns, and in which adjacent page areas are associated with different bank addresses, and during a period of horizontal access in which the two-dimensionally arrayed data is accessed horizontally, the control circuit causes the memory cores (92) within banks selected by the bank addresses to execute normal memory operation corresponding to a normal operation command in response to the normal operation command corresponding to the horizontal access, and further causes a memory core (92) within a refresh target bank other than the horizontal access target bank to execute refresh operation in response to a background refresh command.

    摘要翻译： 提供一种存储器件，存储器件的存储器控​​制器及其存储器系统，其中由存储器件的刷新操作引起的有效带宽的减少已经得到解决。 响应于来自存储器控制器（82）的命令而操作的存储器件具有多个存储体，所述存储体设备分别具有包括存储器单元阵列和解码器的存储器核心（92）并且通过存储体地址选择; 以及控制所述存储体内的所述存储单元阵列的动作的控制电路，所述多个存储体的各存储体基于存储器逻辑空间具有多个页面区域的存储器映射来存储二维排列的数据， 由行地址和行地址选择，其中多个页面区域按行和列排列，并且其中相邻页面区域与不同的库地址相关联，并且在二维地在水平访问期间 阵列数据被水平访问时，控制电路响应于与水平访问相对应的正常操作命令，使得由存储体地址所选择的存储体内的存储器核心（92）执行对应于正常操作命令的正常存储器操作，并且进一步使得 在除了水平访问目标库之外的刷新目标库内的存储器核心（92）响应于ba执行刷新操作 ckground刷新命令。