公开(公告)号：EP0649100B1

公开(公告)日：2003-07-02

申请号：EP94115140.9

申请日：1994-09-26

申请人： Hitachi, Ltd.

发明人： Satoh, Jun ,  Yamagishi, Kazushige ,  Nakashima, Keisuke ,  Katsura, Koyo ,  Miyamoto, Takashi ,  Watabe, Mitsuru ,  Ohmura, Kenichiroh

IPC分类号： G06T1/20 ,  G06F13/16 ,  G06F15/16 ,  G06F13/28

CPC分类号： G09G5/393 ,  G06F1/04 ,  G06F1/12 ,  G06F12/0207 ,  G06F13/1689 ,  G06F13/4243 ,  G06F15/7832 ,  G06T1/60 ,  G09G5/001 ,  G09G5/395 ,  G09G5/399 ,  G09G2320/0252 ,  G09G2350/00 ,  G09G2360/128 ,  G09G2370/10 ,  G11C8/04 ,  G11C8/06 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18

公开(公告)号：EP0649100A3

公开(公告)日：1997-02-26

申请号：EP94115140.9

申请日：1994-09-26

申请人： HITACHI, LTD.

发明人： Satoh, Jun ,  Yamagishi, Kazushige ,  Nakashima, Keisuke ,  Katsura, Koyo ,  Miyamoto, Takashi ,  Watabe, Mitsuru ,  Ohmura, Kenichiroh

IPC分类号： G06F15/80 ,  G06T1/20

CPC分类号： G09G5/393 ,  G06F1/04 ,  G06F1/12 ,  G06F12/0207 ,  G06F13/1689 ,  G06F13/4243 ,  G06F15/7832 ,  G06T1/60 ,  G09G5/001 ,  G09G5/395 ,  G09G5/399 ,  G09G2320/0252 ,  G09G2350/00 ,  G09G2360/128 ,  G09G2370/10 ,  G11C8/04 ,  G11C8/06 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18

摘要： A data processor comprises a bus control circuit (14) adapted to be interfaced with a synchronous DRAM (22) which can be accessed in synchronism with a clock signal (CLK), a plurality of data processing modules (12, 13) coupled to said bus control circuit (14) for producing data and addresses for accessing a memory (22), and a clock driver (16) for feeding intrinsic operation clocks to said data processing modules (12, 13) and for feeding the clock signal for accessing said memory (22) in synchronism with the operations of said data processing modules (12, 13) to be operated by the operation clock signals, to the outside.

公开(公告)号：EP1182640A3

公开(公告)日：2007-09-26

申请号：EP01104157.1

申请日：2001-02-21

申请人： Hitachi, Ltd.

发明人： Nakatsuka, Yasuhiro ,  Shimomura, Tetsuya ,  Jyou, Manabu ,  Morita, Yuichiro ,  Hotta, Takashi ,  Yamagishi, Kazushige ,  Okada, Yukata

IPC分类号： G09G5/36

CPC分类号： G09G5/39 ,  G09G2360/125

摘要： The basic section of the multimedia data-processing system comprises CPU 1100, image display unit 2100, unified memory 1200, system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.

公开(公告)号：EP0649100A2

公开(公告)日：1995-04-19

申请号：EP94115140.9

申请日：1994-09-26

申请人： HITACHI, LTD.

发明人： Satoh, Jun ,  Yamagishi, Kazushige ,  Nakashima, Keisuke ,  Katsura, Koyo ,  Miyamoto, Takashi ,  Watabe, Mitsuru ,  Ohmura, Kenichiroh

IPC分类号： G06F15/80 ,  G06T1/20

CPC分类号： G09G5/393 ,  G06F1/04 ,  G06F1/12 ,  G06F12/0207 ,  G06F13/1689 ,  G06F13/4243 ,  G06F15/7832 ,  G06T1/60 ,  G09G5/001 ,  G09G5/395 ,  G09G5/399 ,  G09G2320/0252 ,  G09G2350/00 ,  G09G2360/128 ,  G09G2370/10 ,  G11C8/04 ,  G11C8/06 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18

摘要： A data processor comprises a bus control circuit (14) adapted to be interfaced with a synchronous DRAM (22) which can be accessed in synchronism with a clock signal (CLK), a plurality of data processing modules (12, 13) coupled to said bus control circuit (14) for producing data and addresses for accessing a memory (22), and a clock driver (16) for feeding intrinsic operation clocks to said data processing modules (12, 13) and for feeding the clock signal for accessing said memory (22) in synchronism with the operations of said data processing modules (12, 13) to be operated by the operation clock signals, to the outside.

摘要翻译： 数据处理器包括适于与可与时钟信号（CLK）同步访问的同步DRAM（22）接口的总线控制电路（14），与所述时钟信号（CLK）耦合的多个数据处理模块（12,13） 总线控制电路（14），用于产生用于访问存储器（22）的数据和地址;以及时钟驱动器（16），用于将固有操作时钟馈送到所述数据处理模块（12,13），并且用于馈送用于访问所述存储器 存储器（22）与由操作时钟信号操作的所述数据处理模块（12,13）的操作同步到外部。

公开(公告)号：EP1182640A2

公开(公告)日：2002-02-27

申请号：EP01104157.1

申请日：2001-02-21

申请人： Hitachi, Ltd.

发明人： Nakatsuka, Yasuhiro ,  Shimomura, Tetsuya ,  Jyou, Manabu ,  Morita, Yuichiro ,  Hotta, Takashi ,  Yamagishi, Kazushige ,  Okada, Yukata

IPC分类号： G09G5/36

CPC分类号： G09G5/39 ,  G09G2360/125

摘要： The basic section of the multimedia data-processing system comprises CPU 1100, image display unit 2100, unified memory 1200, system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.

摘要翻译： 多媒体数据处理系统的基本部分包括CPU 1100，图像显示单元2100，统一存储器1200，系统总线1920和连接到系统总线的设备1300,1400和1500。 在这种配置中，CPU形成在安装在包括指令处理单元1110和显示控制单元1140的单个硅晶片上的LSI上。主存储区域1210和显示区域1220被存储在统一存储器内。 与用于连接LSI和输入/输出设备的系统总线独立地提供用于连接对应的LSI和统一存储器的统一存储器端口1910。 统一的存储器端口可以比系统总线更快地驱动。