公开(公告)号：EP0454447A3

公开(公告)日：1993-12-08

申请号：EP91303709.9

申请日：1991-04-24

申请人： HITACHI, LTD.

发明人： Oguchi, Satoshi ,  Ishihara, Masamichi ,  Ito, Kazuya ,  Murakami, Gen ,  Anjo, Ichiro ,  Sakuta, Toshiyuki ,  Yamaguchi, Yasunori ,  Kasama, Yasuhiro ,  Udagawa, Tetsu ,  Miyamoto, Eiji ,  Matsuno, Youichi ,  Satoh, Hiroshi ,  Nozoe, Atsusi

IPC分类号： H01L25/065 ,  H01L23/495 ,  G06F11/20

CPC分类号： H01L24/06 ,  G11C5/00 ,  G11C5/02 ,  G11C5/06 ,  H01L23/4951 ,  H01L23/49537 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/1029 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01055 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.

公开(公告)号：EP0454447A2

公开(公告)日：1991-10-30

申请号：EP91303709.9

申请日：1991-04-24

申请人： HITACHI, LTD.

发明人： Oguchi, Satoshi ,  Ishihara, Masamichi ,  Ito, Kazuya ,  Murakami, Gen ,  Anjo, Ichiro ,  Sakuta, Toshiyuki ,  Yamaguchi, Yasunori ,  Kasama, Yasuhiro ,  Udagawa, Tetsu ,  Miyamoto, Eiji ,  Matsuno, Youichi ,  Satoh, Hiroshi ,  Nozoe, Atsusi

IPC分类号： H01L25/065 ,  H01L23/495 ,  G06F11/20

CPC分类号： H01L24/06 ,  G11C5/00 ,  G11C5/02 ,  G11C5/06 ,  H01L23/4951 ,  H01L23/49537 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/1029 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01055 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.

摘要翻译： 一对DRAM芯片1A和1B通过诸如引线框架之间的布线装置彼此相对地安装，引线框架与外部端子3B基本上是一体的。 然后，这些DRAM芯片和引线框架通过常规的引线键合方法连接在一起。 层叠这样连接的DRAM芯片和引线框架的多对，引线框架的相应引线共同连接以形成层叠体。 这样安装的多个DRAM芯片根据预定的芯片选择信号选择性地被激活。 此外，能够通过利用上述芯片安装方法将能够正常部分功能的部分DRAM芯片组合在一起以构成单个DRAM封装。