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14 条记录 (耗时 0.012 秒)

    Information processing apparatus and information processing system
    3.
    发明公开
    Information processing apparatus and information processing system 失效
    信息处理设备和信息处理系统

    公开(公告)号：EP0557997A3

    公开(公告)日：1995-05-24

    申请号：EP93102966.4

    申请日：1993-02-25

    申请人： HITACHI, LTD.

    发明人： Asai, Mitsuo ,  Shibata, Katsunari ,  Sato, Yuji ,  Yamada, Minoru ,  Sakaguchi, Takahiro ,  Hashimoto, Masashi

    IPC分类号： G06F15/80

    CPC分类号： H04N19/436 ,  G06N3/063 ,  G06N3/10

    摘要： An information processing apparatus is made up of a plurality of modules (1, 2, 3, 4, 125, 126, 127, 128). One module is made up of a functional block for rapidly operating a scalar product and a control unit for controlling the functional block. The module operates itself in an SIMD manner. The plurality of modules are connected so as to communicate a signal with each other. The plurality of modules operate in an MIMD manner. Inside of one module, the strong fault tolerant parts such as a neuron processor (204) and a memory (202) are integrated on an integrated circuit substrate. The weak fault tolerant parts such as a control unit is mounted on the integrated circuit substrate by means of a silicon on silicon technique.

    摘要翻译： 信息处理设备由多个模块（1,2,3,4,125,126,127,128）组成。 一个模块由用于快速操作标量产品的功能块和用于控制功能块的控制单元组成。 该模块以SIMD方式运行。 多个模块被连接以便彼此传递信号。 多个模块以MIMD方式操作。 在一个模块内部，诸如神经元处理器（204）和存储器（202）的强大容错部件被集成在集成电路基板上。 借助于硅上硅技术将诸如控制单元的弱容错部件安装在集成电路衬底上。

    Information processing apparatus and information processing system
    4.
    发明公开
    Information processing apparatus and information processing system 失效
    Informationsverarbeitungsanlage和系统。

    公开(公告)号：EP0557997A2

    公开(公告)日：1993-09-01

    申请号：EP93102966.4

    申请日：1993-02-25

    申请人： HITACHI, LTD.

    发明人： Asai, Mitsuo ,  Shibata, Katsunari ,  Sato, Yuji ,  Yamada, Minoru ,  Sakaguchi, Takahiro ,  Hashimoto, Masashi

    IPC分类号： G06F15/80

    CPC分类号： H04N19/436 ,  G06N3/063 ,  G06N3/10

    摘要： An information processing apparatus is made up of a plurality of modules (1, 2, 3, 4, 125, 126, 127, 128). One module is made up of a functional block for rapidly operating a scalar product and a control unit for controlling the functional block. The module operates itself in an SIMD manner. The plurality of modules are connected so as to communicate a signal with each other. The plurality of modules operate in an MIMD manner. Inside of one module, the strong fault tolerant parts such as a neuron processor (204) and a memory (202) are integrated on an integrated circuit substrate. The weak fault tolerant parts such as a control unit is mounted on the integrated circuit substrate by means of a silicon on silicon technique.

    摘要翻译： 信息处理装置由多个模块（1,2,3,4,125,126,127,128）构成。 一个模块由用于快速操作标量产品的功能块和用于控制功能块的控制单元组成。 该模块以SIMD方式运行。 多个模块被连接以便彼此通信信号。 多个模块以MIMD方式操作。 在一个模块内部，诸如神经元处理器（204）和存储器（202）的强容错部件集成在集成电路基板上。 诸如控制单元之类的弱容错部件通过硅硅技术安装在集成电路基板上。

    Neural computer
    6.
    发明公开
    Neural computer 失效
    神经元Rechner

    公开(公告)号：EP0378115A2

    公开(公告)日：1990-07-18

    申请号：EP90100171.9

    申请日：1990-01-04

    申请人： HITACHI, LTD.

    发明人： Masuda, Noboru ,  Yasunaga, Moritoshi ,  Yamada, Minoru ,  Masaki, Akira ,  Asai, Mitsuo ,  Hirai, Yuzo ,  Yagyu, Masayoshi ,  Hayashi, Takehisa ,  Doi, Toshio ,  Ishibashi, Kenichi

    IPC分类号： G06F15/80

    CPC分类号： G06N3/063 ,  G06N3/04

    摘要： An information processing system includes a plurality of functional blocks (neurons) (100) and a data bus (300) for transmitting in common the outputs of the individual functional blocks (neurons). Data transaction among the functional blocks (neurons) is performed through the data bus on the time-division basis. For preventing the outputs from conflicting or competition, addresses are assigned to the individual blocks (neurons), respectively, so that only the functional block (neuron) having the own address designated by the address signal supplied through an address bus (302) outputs data signal onto the data bus, while the other functional blocks (neurons) receive the information on the data bus as the signal originating in the functional block whose address is designated at that time point. The addresses are sequentially changed. During a round of the addresses signals, data are transmitted from given functional blocks (neurons) to other given functional blocks (neurons).

    摘要翻译： 信息处理系统包括用于各个功能块（神经元）的输出的多个功能块（神经元）（100）和数据总线（300）。 功能块（神经元）之间的数据交换通过时分基础上的数据总线进行。 为了防止输出冲突或竞争，分别将地址分配给各个块（神经元），使得仅具有通过地址总线（302）提供的地址信号指定的自己的地址的功能块（神经元）输出数据 信号到数据总线上，而其他功能块（神经元）接收数据总线上的信息作为起始于在该时间点指定地址的功能块的信号。 地址顺序更改。 在一轮地址信号期间，数据从给定的功能块（神经元）发送到其他给定的功能块（神经元）。

    Neural computer
    9.
    发明公开
    Neural computer 失效
    神经电脑

    公开(公告)号：EP0378115A3

    公开(公告)日：1993-12-22

    申请号：EP90100171.9

    申请日：1990-01-04

    申请人： HITACHI, LTD.

    发明人： Masuda, Noboru ,  Yasunaga, Moritoshi ,  Yamada, Minoru ,  Masaki, Akira ,  Asai, Mitsuo ,  Hirai, Yuzo ,  Yagyu, Masayoshi ,  Hayashi, Takehisa ,  Doi, Toshio ,  Ishibashi, Kenichi

    IPC分类号： G06F15/80

    CPC分类号： G06N3/063 ,  G06N3/04

    摘要： An information processing system includes a plurality of functional blocks (neurons) (100) and a data bus (300) for transmitting in common the outputs of the individual functional blocks (neurons). Data transaction among the functional blocks (neurons) is performed through the data bus on the time-division basis. For preventing the outputs from conflicting or competition, addresses are assigned to the individual blocks (neurons), respectively, so that only the functional block (neuron) having the own address designated by the address signal supplied through an address bus (302) outputs data signal onto the data bus, while the other functional blocks (neurons) receive the information on the data bus as the signal originating in the functional block whose address is designated at that time point. The addresses are sequentially changed. During a round of the addresses signals, data are transmitted from given functional blocks (neurons) to other given functional blocks (neurons).