摘要:
There is provided a control apparatus of an AC motor (2) capable of performing stable torque control even over the entire running region of the AC motor. Structurally, a feedback control system (9, 8) for controlling the magnitude of motor primary current, a feedback control system (8, 17) for controlling the exciting component of motor primary current and a feedback control system (8, 18) for controlling the torque component of motor primary current are provided. Torque control is effected by a vector control system (4, 5, 6, 7, 8, 9) in the low speed running region and torque control is effected by a slip frequency control system (16, 10, 19, 20, 21, 22, 23) in the high speed running region, so that torque can be controlled excellently over the entire running region.
摘要:
There is provided a control apparatus of an AC motor (2) capable of performing stable torque control even over the entire running region of the AC motor. Structurally, a feedback control system (9, 8) for controlling the magnitude of motor primary current, a feedback control system (8, 17) for controlling the exciting component of motor primary current and a feedback control system (8, 18) for controlling the torque component of motor primary current are provided. Torque control is effected by a vector control system (4, 5, 6, 7, 8, 9) in the low speed running region and torque control is effected by a slip frequency control system (16, 10, 19, 20, 21, 22, 23) in the high speed running region, so that torque can be controlled excellently over the entire running region.
摘要:
In a multi series pulse width modulation inverter arrangement, an inverter arrangement which can continue the inverter operation, in particular, by preventing an overcurrent caused by an erroneous firing of a switching element therein is provided. The multi series inverter arrangement is constituted to be operative in three level mode and in two level mode. Even when an erroneous firing thereof due to noise is generated, the operation of the inverter unit (4) can be continued, the overcurrent due to the erroneous firing is eliminated, the present inverter arrangement can be used under a severe noise environment and outputs an AC output having a small amount of higher harmonics, moreover when the inverter arrangement is operating under a three level mode in a low efficiency region, the operating mode of the inverter arrangement is positively switched from the three level mode to the two level mode, thereby the operating efficiency of the inverter arrangement is enhanced.
摘要:
In a multiprocessor system having a main memory (10) and a plurality of processors (12) connected through common address bus (13), data bus (14) and answer bus (15) for the data transfer, a data transmission apparatus is provided for each of the main memory and the processors and includes bus request control lines (13-1, 14-1, 15-1) for transferring bus request signals and bus control signals and a bus controller (17) for separately controlling selections of the address bus, the data bus and the answer bus in response to the signals on the bus request control lines and the request signal. Overlapped processing such as data write and data write answer or data read and data read answer in one cycle is permitted.
摘要:
A virtual storage data processing system having an address translation unit (75) shared by a plurality of processors, located in a memory control unit (12) connected to a main memory (10) is disclosed. One of the plurality of processors is a job processor (40) which accesses the main memory with a virtual address to execute an instruction and includes a cache memory (41, 42) which is accessed with a virtual address. One of the plurality of processors is a file processor, (22) which accesses the main memory with a virtual address to transfer data between the main memory and an external memory (20). The cache memory receives the virtual address when the file processor writes to the main memory and if it contains a data block corresponding to the virtual address, it invalidates the corresponding data block. The address translation unit translates the address differently for the access from the file processor and the accesses from other processors.
摘要:
A central processing unit for executing instructions of variable length in which an operand specifier for specifying the addressing mode of an operand is independent of an operation code for ascertaining the kind of an operation and the number of operands. Each operand specifier is formed of one or more data bytes, and has a stop bit flag indicating whether or not the particular operand specifier is the last operand specifier. By adding the stop bit flag, the operand specifier can be shared, and different processing can be executed with an identical operation code. In a case where, when operation code decoding means has provided an output indicative of the last operand, the stop bit flag is not detected in the corresponding operand specifier, the corresponding instruction is detected as an error.
摘要:
A central processing unit for executing instructions of variable length in which an operand specifier for specifying the addressing mode of an operand is independent of an operation code for ascertaining the kind of an operation and the number of operands. Each operand specifier is formed of one or more data bytes, and has a stop bit flag indicating whether or not the particular operand specifier is the last operand specifier. By adding the stop bit flag, the operand specifier can be shared, and different processing can be executed with an identical operation code. In a case where, when operation code decoding means has provided an output indicative of the last operand, the stop bit flag is not detected in the corresponding operand specifier, the corresponding instruction is detected as an error.
摘要:
In a multi series pulse width modulation inverter arrangement, an inverter arrangement which can continue the inverter operation, in particular, by preventing an overcurrent caused by an erroneous firing of a switching element therein is provided. The multi series inverter arrangement is constituted to be operative in three level mode and in two level mode. Even when an erroneous firing thereof due to noise is generated, the operation of the inverter unit (4) can be continued, the overcurrent due to the erroneous firing is eliminated, the present inverter arrangement can be used under a severe noise environment and outputs an AC output having a small amount of higher harmonics, moreover when the inverter arrangement is operating under a three level mode in a low efficiency region, the operating mode of the inverter arrangement is positively switched from the three level mode to the two level mode, thereby the operating efficiency of the inverter arrangement is enhanced.