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1.发明公开Inverter arrangement and AC motor driving system 失效Wechselrichteranordnung und AnsteuersystemfürWechselstrommotor。
公开(公告)号：EP0512531A2
公开(公告)日：1992-11-11
申请号：EP92107689.9
申请日：1992-05-07
发明人： Matsui, Takayuki , Horie, Akira , Kawakami, Tetsuya , Saitoh, Syuuji , Toyota, Eiichi , Sakata,Kazuhiro , Tsuboi,Takashi , Nakamura, Kiyoshi , Nakata, Kiyoshi , Tsutsui, Yoshio , Tanamachi, Tokunosuke
CPC分类号： H02M7/487 , B60L3/0023 , B60L9/22 , B60L2200/26 , B60L2210/20 , H02H7/1225 , Y02T10/725
摘要： In a multi series pulse width modulation inverter arrangement, an inverter arrangement which can continue the inverter operation, in particular, by preventing an overcurrent caused by an erroneous firing of a switching element therein is provided. The multi series inverter arrangement is constituted to be operative in three level mode and in two level mode. Even when an erroneous firing thereof due to noise is generated, the operation of the inverter unit (4) can be continued, the overcurrent due to the erroneous firing is eliminated, the present inverter arrangement can be used under a severe noise environment and outputs an AC output having a small amount of higher harmonics, moreover when the inverter arrangement is operating under a three level mode in a low efficiency region, the operating mode of the inverter arrangement is positively switched from the three level mode to the two level mode, thereby the operating efficiency of the inverter arrangement is enhanced.
摘要翻译： 在多串联脉宽调制逆变器装置中，提供了一种能够继续逆变器操作的逆变器装置，特别是通过防止由其中的开关元件的错误点火引起的过电流。 多串联逆变器装置构成为在三电平模式和二电平模式下工作。 即使当由于噪声而产生其错误的点火时，逆变器单元（4）的操作也可以继续，由于消除了由于错误的点火引起的过电流，本逆变器装置可以在恶劣的环境下使用并输出 交流输出具有少量的高次谐波，而且当逆变器装置在三电平模式下工作在低效率区域时，逆变器装置的工作模式从三电平模式正向切换到二电平模式 提高了逆变器装置的运行效率。
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公开(公告)号：EP0512531A3
公开(公告)日：1992-12-09
申请号：EP92107689.9
申请日：1992-05-07
发明人： Matsui, Takayuki , Horie, Akira , Kawakami, Tetsuya , Saitoh, Syuuji , Toyota, Eiichi , Sakata,Kazuhiro , Tsuboi,Takashi , Nakamura, Kiyoshi , Nakata, Kiyoshi , Tsutsui, Yoshio , Tanamachi, Tokunosuke
CPC分类号： H02M7/487 , B60L3/0023 , B60L9/22 , B60L2200/26 , B60L2210/20 , H02H7/1225 , Y02T10/725
摘要： In a multi series pulse width modulation inverter arrangement, an inverter arrangement which can continue the inverter operation, in particular, by preventing an overcurrent caused by an erroneous firing of a switching element therein is provided. The multi series inverter arrangement is constituted to be operative in three level mode and in two level mode. Even when an erroneous firing thereof due to noise is generated, the operation of the inverter unit (4) can be continued, the overcurrent due to the erroneous firing is eliminated, the present inverter arrangement can be used under a severe noise environment and outputs an AC output having a small amount of higher harmonics, moreover when the inverter arrangement is operating under a three level mode in a low efficiency region, the operating mode of the inverter arrangement is positively switched from the three level mode to the two level mode, thereby the operating efficiency of the inverter arrangement is enhanced.
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公开(公告)号：EP0063334A1
公开(公告)日：1982-10-27
申请号：EP82103065.7
申请日：1982-04-08
发明人： Fukunaga, Yasushi Moriyama-Apartment House 503 , Bandoh, Tadaaki , Hiraoka, Ryosei , Matsumoto, Hidekazu Moriyama-Apartment House 102 , Ide, Jushi , Kawakami, Tetsuya
IPC分类号： G06F13/36
CPC分类号： G06F13/374
摘要： In a multiprocessor system having a main memory (10) and a plurality of processors (12) connected through common address bus (13), data bus (14) and answer bus (15) for the data transfer, a data transmission apparatus is provided for each of the main memory and the processors and includes bus request control lines (13-1, 14-1, 15-1) for transferring bus request signals and bus control signals and a bus controller (17) for separately controlling selections of the address bus, the data bus and the answer bus in response to the signals on the bus request control lines and the request signal. Overlapped processing such as data write and data write answer or data read and data read answer in one cycle is permitted.
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公开(公告)号：EP0052370A2
公开(公告)日：1982-05-26
申请号：EP81109719.5
申请日：1981-11-16
发明人： Fukunaga, Yasushi , Bandoh, Tadaaki , Matsumoto, Hidekazu , Hiraoka, Ryosei , Ide, Jushi , Kato, Takeshi , Kawakami, Tetsuya
CPC分类号： G06F12/1081 , G06F12/0833 , G06F12/1045
摘要： A virtual storage data processing system having an address translation unit (75) shared by a plurality of processors, located in a memory control unit (12) connected to a main memory (10) is disclosed. One of the plurality of processors is a job processor (40) which accesses the main memory with a virtual address to execute an instruction and includes a cache memory (41, 42) which is accessed with a virtual address. One of the plurality of processors is a file processor, (22) which accesses the main memory with a virtual address to transfer data between the main memory and an external memory (20). The cache memory receives the virtual address when the file processor writes to the main memory and if it contains a data block corresponding to the virtual address, it invalidates the corresponding data block. The address translation unit translates the address differently for the access from the file processor and the accesses from other processors.
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公开(公告)号：EP0073424A3
公开(公告)日：1984-05-23
申请号：EP82107598
申请日：1982-08-19
发明人： Fukunaga, Yasushi , Bandoh, Tadaaki , Hirasawa, Kotaro , Matsumoto, Hidekazu , Ide, Jushi , Katoh, Takeshi , Nakanishi, Hiroaki , Kawakami, Tetsuya , Hiraoka, Ryosei
CPC分类号： G06F9/30167 , G06F9/30152 , G06F9/3016
摘要： A central processing unit for executing instructions of variable length in which an operand specifier for specifying the addressing mode of an operand is independent of an operation code for ascertaining the kind of an operation and the number of operands. Each operand specifier is formed of one or more data bytes, and has a stop bit flag indicating whether or not the particular operand specifier is the last operand specifier. By adding the stop bit flag, the operand specifier can be shared, and different processing can be executed with an identical operation code. In a case where, when operation code decoding means has provided an output indicative of the last operand, the stop bit flag is not detected in the corresponding operand specifier, the corresponding instruction is detected as an error.
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6.发明公开
公开(公告)号：EP0073424A2
公开(公告)日：1983-03-09
申请号：EP82107598.3
申请日：1982-08-19
发明人： Fukunaga, Yasushi , Bandoh, Tadaaki , Hirasawa, Kotaro , Matsumoto, Hidekazu , Ide, Jushi , Katoh, Takeshi , Nakanishi, Hiroaki , Kawakami, Tetsuya , Hiraoka, Ryosei
CPC分类号： G06F9/30167 , G06F9/30152 , G06F9/3016
摘要： A central processing unit for executing instructions of variable length in which an operand specifier for specifying the addressing mode of an operand is independent of an operation code for ascertaining the kind of an operation and the number of operands. Each operand specifier is formed of one or more data bytes, and has a stop bit flag indicating whether or not the particular operand specifier is the last operand specifier. By adding the stop bit flag, the operand specifier can be shared, and different processing can be executed with an identical operation code. In a case where, when operation code decoding means has provided an output indicative of the last operand, the stop bit flag is not detected in the corresponding operand specifier, the corresponding instruction is detected as an error.
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公开(公告)号：EP0052370B1
公开(公告)日：1987-11-04
申请号：EP81109719.5
申请日：1981-11-16
发明人： Fukunaga, Yasushi , Bandoh, Tadaaki , Matsumoto, Hidekazu , Hiraoka, Ryosei , Ide, Jushi , Kato, Takeshi , Kawakami, Tetsuya
CPC分类号： G06F12/1081 , G06F12/0833 , G06F12/1045
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公开(公告)号：EP0063334B1
公开(公告)日：1985-11-21
申请号：EP82103065.7
申请日：1982-04-08
发明人： Fukunaga, Yasushi Moriyama-Apartment House 503 , Bandoh, Tadaaki , Hiraoka, Ryosei , Matsumoto, Hidekazu Moriyama-Apartment House 102 , Ide, Jushi , Kawakami, Tetsuya
IPC分类号： G06F13/36
CPC分类号： G06F13/374
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公开(公告)号：EP0052370A3
公开(公告)日：1984-03-28
申请号：EP81109719
申请日：1981-11-16
发明人： Fukunaga, Yasushi , Bandoh, Tadaaki , Matsumoto, Hidekazu , Hiraoka, Ryosei , Ide, Jushi , Kato, Takeshi , Kawakami, Tetsuya
CPC分类号： G06F12/1081 , G06F12/0833 , G06F12/1045
摘要： A virtual storage data processing system having an address translation unit (75) shared by a plurality of processors, located in a memory control unit (12) connected to a main memory (10) is disclosed. One of the plurality of processors is a job processor (40) which accesses the main memory with a virtual address to execute an instruction and includes a cache memory (41, 42) which is accessed with a virtual address. One of the plurality of processors is a file processor, (22) which accesses the main memory with a virtual address to transfer data between the main memory and an external memory (20). The cache memory receives the virtual address when the file processor writes to the main memory and if it contains a data block corresponding to the virtual address, it invalidates the corresponding data block. The address translation unit translates the address differently for the access from the file processor and the accesses from other processors.
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10.发明公开AC motor control apparatus and control apparatus of electric rolling stock using the same 失效交流电机控制装置及使用该电动滚筒的控制装置
公开(公告)号：EP0536569A3
公开(公告)日：1996-04-10
申请号：EP92115826.7
申请日：1992-09-16
发明人： Matsui, Takayuki , Horie, Akira , Saito, Shuji , Toyota, Eiichi , Sakata, Kazuhiro , Ando, Takeshi , Tsuboi, Takashi , Kawakami, Tetsuya , Takaku, Toshihiko
CPC分类号： B60L15/025 , B60L9/16 , B60L9/22 , B60L11/1803 , B60L2200/26 , B60L2220/12 , H02P21/09 , Y02T10/643 , Y02T10/7005 , Y02T10/7258
摘要： There is provided a control apparatus of an AC motor (2) capable of performing stable torque control even over the entire running region of the AC motor. Structurally, a feedback control system (9, 8) for controlling the magnitude of motor primary current, a feedback control system (8, 17) for controlling the exciting component of motor primary current and a feedback control system (8, 18) for controlling the torque component of motor primary current are provided. Torque control is effected by a vector control system (4, 5, 6, 7, 8, 9) in the low speed running region and torque control is effected by a slip frequency control system (16, 10, 19, 20, 21, 22, 23) in the high speed running region, so that torque can be controlled excellently over the entire running region.
摘要翻译： 提供了一种即使在交流电动机的整个运行区域上能够执行稳定转矩控制的交流电动机（2）的控制装置。 在结构上，用于控制电动机初级电流的大小的反馈控制系统（9,8），用于控制电动机初级电流的激励分量的反馈控制系统（8,17）和用于控制电机初级电流的反馈控制系统（8,18） 提供电机初级电流的转矩分量。 转矩控制由低速行驶区域中的矢量控制系统（4,5,6,7,8,9）进行，转矩控制由转差控制系统（16,10,19,20,21， 22,23），从而能够在整个行驶区域上良好地控制转矩。
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