摘要:
An image control apparatus in a television receiver, wherein after determining the frequency characteristic of an inputted video signal, when a high frequency band of the frequency characteristic has been raised above a predetermined level, the image quality is enhanced after performing waveform equalization on the video signal to cancel an impression of a dim image, given to the visual sense, and on the other hand, when the high frequency band of the inputted video signal has been lowered, noise reduction is performed after waveform equalization to further degrade the image quality for preventing deterioration of the S/N ratio, thereby usually providing appropriate images. The image control apparatus includes a waveform equalizer (101), a distorted waveform extraction control unit (102), a noise reduction circuit (103), and an image quality control unit (104). The waveform equalizer (101) receives an inputted video signal, equalizes waveform of the video signal, and outputs the waveform equalized video signal. The distorted waveform extraction control unit (102) detects distorted waveform from the output of the waveform equalizer and controls the waveform equalizer to perform waveform equalization suitable for the inputted video signal. It also controls the noise reduction circuit (103) and the image quality control unit (104) in accordance with changes in the frequency characteristic of the video signal before and after waveform equalization to intensify the noise reduction for degrading the image quality, when the high frequency band of the frequency characteristic of the input signal has been lowered, and, contrarily, to debilitate or stop the noise reduction for enhancing the image quality, when the high frequency band has been raised.
摘要:
To provide an image which is matched with an aspect ratio of a screen of a display unit by compressing and enlarging the whole of the image to a desired size. A video signal is sequentially written into a field memory in response to a write clock from an input terminal (118). A clock generating circuit (119) supplies the field memory (103) with a read clock having a frequency which is about 4/3 times as high as that of the write clock. A vertical enlargement control circuit (110) reads a video signal from the field memory (103) with a line period corresponding to a magnification factor and inhibits writing to a one-line memory (105) with the same period to provide a line delayed output for an output signal from the field memory (13). A vertical interpolating circuit (106) generates a scanning line signal by an interpolation operation in accordance with a control signal from the vertical enlargement control circuit (110).
摘要:
An arrangement to automatically change between a scrambled digital data output and descrambled digital data output of a receiver by inserting a control signal conforming to a program provider's policy into a transmission signal. In a receiving side, a descrambler descrambles a channel-decoded signal, a demultiplexer demultiplexes the multiplexed signal from the descrambler into encoded video and audio data for output to a source decoder, and extracts the control information inserted in the transmitting side for output to a switch or CPU. The CPU decrypts a control signal from the control information extracted by the demultiplexer to determine whether the scrambled digital signal or descrambled digital signal is appropriate for output, and outputs a changeover control signal depending on the result of decryption. A switch selects the output of a scrambled digital signal from a stage prior to the descrambler, or a descrambled digital signal from a stage subsequent to the descrambler, depending on the changeover control signal from the CPU. Thereby, a scrambled digital signal output or descrambled digital signal output can automatically be changed over depending on a program provider's policy.
摘要:
An arrangement to automatically change between a scrambled digital data output and descrambled digital data output of a receiver by inserting a control signal conforming to a program provider's policy into a transmission signal. In a receiving side, a descrambler descrambles a channel-decoded signal, a demultiplexer demultiplexes the multiplexed signal from the descrambler into encoded video and audio data for output to a source decoder, and extracts the control information inserted in the transmitting side for output to a switch or CPU. The CPU decrypts a control signal from the control information extracted by the demultiplexer to determine whether the scrambled digital signal or descrambled digital signal is appropriate for output, and outputs a changeover control signal depending on the result of decryption. A switch selects the output of a scrambled digital signal from a stage prior to the descrambler, or a descrambled digital signal from a stage subsequent to the descrambler, depending on the changeover control signal from the CPU. Thereby, a scrambled digital signal output or descrambled digital signal output can automatically be changed over depending on a program provider's policy.
摘要:
An amplifier circuit using MOS transistors (5, 8, 22). The load to be connected to an amplifying element (5) of the amplifier circuit is formed by a C-MOS transistor (8, 22) having a P-MOS transistor (8) and an N-MOS transistor (22).
摘要:
To provide an image which is matched with an aspect ratio of a screen of a display unit by compressing and enlarging the whole of the image to a desired size. A video signal is sequentially written into a field memory in response to a write clock from an input terminal (118). A clock generating circuit (119) supplies the field memory (103) with a read clock having a frequency which is about 4/3 times as high as that of the write clock. A vertical enlargement control circuit (110) reads a video signal from the field memory (103) with a line period corresponding to a magnification factor and inhibits writing to a one-line memory (105) with the same period to provide a line delayed output for an output signal from the field memory (13). A vertical interpolating circuit (106) generates a scanning line signal by an interpolation operation in accordance with a control signal from the vertical enlargement control circuit (110).
摘要:
A signal converting circuit is disclosed for converting a television signal for 2:1 interlaced scanning system to another television signal for 1:1 non-interlaced scanning system using line memories (3, 4 5) for storing image data of two adjacent scanning lines of a present field and field memories (23, 24) for storing image data of a last occurring field. An interpolation signal (10) is produced by controlling a value of the televisions signal (16, 17) of the two adjacent scanning lines in response to the television signal (29) of the two adjacent scanning lines in the present field and the television signal of a scanning line positioned between the two adjacent scanning lines in the last occurring field.