公开(公告)号：EP2839508A1

公开(公告)日：2015-02-25

申请号：EP13778187.8

申请日：2013-04-05

申请人： HRL Laboratories, LLC

发明人： BROWN, David F. ,  MICOVIC, Miroslav

IPC分类号： H01L29/778 ,  H01L21/335

CPC分类号： H01L29/205 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/42316 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

摘要： A device and a method of making a graded barrier layer on a group III-N HFET wherein the device has a group III-nitride buffer deposited on a substrate; and a group III-nitride heterostructure disposed on a surface of the group III-nitride buffer, wherein the group III-nitride heterostructure has a group III-nitride channel and a group III-nitride barrier layer disposed on a surface of the group III-nitride channel, the group III-nitride barrier layer including Al as one of its constituent group III elements, the Al having a mole fraction which varies at least throughout a portion of said group III-nitride barrier layer.

公开(公告)号：EP2737537B1

公开(公告)日：2019-12-25

申请号：EP12819630.0

申请日：2012-06-19

申请人： HRL Laboratories, LLC

发明人： CHU, Rongming ,  BROWN, David F. ,  CHEN, Xu ,  WILLIAMS, Adam J. ,  BOUTROS, Karim S.

IPC分类号： H01L29/778 ,  H01L21/335

公开(公告)号：EP3055885A1

公开(公告)日：2016-08-17

申请号：EP13894581.1

申请日：2013-09-30

申请人： HRL Laboratories, LLC

发明人： CHU, Rongming ,  BROWN, David F. ,  WILLIAMS, Adam J.

IPC分类号： H01L29/778 ,  H01L21/335

CPC分类号： H01L29/66462 ,  H01L29/2003 ,  H01L29/2006 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/513 ,  H01L29/66522 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/78

摘要： A III-nitride transistor includes a III-nitride channel layer, a barrier layer over the channel layer, the barrier layer having a thickness of 1 to 10 nanometers, a dielectric layer on top of the barrier layer, a source electrode contacting the channel layer, a drain electrode contacting the channel layer, a gate trench extending through the dielectric layer and barrier layer and having a bottom located within the channel layer, a gate insulator lining the gate trench and extending over the dielectric layer, and a gate electrode in the gate trench and extending partially toward the source and the drain electrodes to form an integrated gate field-plate, wherein a distance between an interface of the channel layer and the barrier layer and the bottom of the gate trench is greater than 0 nm and less than or equal to 5 nm.

公开(公告)号：EP3053196A1

公开(公告)日：2016-08-10

申请号：EP14847483.6

申请日：2014-09-16

申请人： HRL Laboratories, LLC

发明人： CHU, Rongming ,  CHEN, Mary Y. ,  LI, Zijian "Ray" ,  BOUTROS, Karim S. ,  CHEN, Xu ,  BROWN, David F. ,  WILLIAMS, Adam J.

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7827 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66666 ,  H01L29/7783 ,  H01L29/7786

摘要： A field-effect transistor (FET) includes a plurality of semiconductor layers, a source electrode and a drain electrode contacting one of the semiconductor layers, a first dielectric layer on a portion of a top semiconductor surface between the source and drain electrodes, a first trench extending through the first dielectric layer and having a bottom located on a top surface or within one of the semiconductor layers, a second dielectric layer lining the first trench and covering a portion of the first dielectric layer, a third dielectric layer over the semiconductor layers, the first dielectric layer, and the second dielectric layer, a second trench extending through the third dielectric layer and having a bottom located in the first trench on the second dielectric layer and extending over a portion of the second dielectric, and a gate electrode filling the second trench.

公开(公告)号：EP2737537A1

公开(公告)日：2014-06-04

申请号：EP12819630.0

申请日：2012-06-19

申请人： HRL Laboratories, LLC

发明人： CHU, Rongming ,  BROWN, David F. ,  CHEN, Xu ,  WILLIAMS, Adam J. ,  BOUTROS, Karim S.

IPC分类号： H01L29/772 ,  H01L21/335

摘要： A field effect transistor (FET) includes a III-Nitride channel layer, a III-Nitride barrier layer on the channel layer, wherein the barrier layer has an energy bandgap greater than the channel layer, a source electrode electrically coupled to one of the III-Nitride layers, a drain electrode electrically coupled to one of the III-Nitride layers, a gate insulator layer stack for electrically insulating a gate electrode from the barrier layer and the channel layer, the gate insulator layer stack including an insulator layer, such as SiN, and an AlN layer, the gate electrode in a region between the source electrode and the drain electrode and in contact with the insulator layer, and wherein the AlN layer is in contact with one of the III-Nitride layers.