公开(公告)号：EP2737537B1

公开(公告)日：2019-12-25

申请号：EP12819630.0

申请日：2012-06-19

申请人： HRL Laboratories, LLC

发明人： CHU, Rongming ,  BROWN, David F. ,  CHEN, Xu ,  WILLIAMS, Adam J. ,  BOUTROS, Karim S.

IPC分类号： H01L29/778 ,  H01L21/335

公开(公告)号：EP3140868A1

公开(公告)日：2017-03-15

申请号：EP15789087.2

申请日：2015-04-22

申请人： HRL Laboratories, LLC

发明人： CHU, Rongming ,  CHEN, Xu

IPC分类号： H01L29/66 ,  H01L21/318

CPC分类号： H01L21/0217 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L23/291 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/7787 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure comprising a layer of a III-N material and at least a portion of said layer being covered by a passivation layer, wherein the passivation layer comprises a first layer of SiN formed on said at least a portion of said III-N material layer and a second layer of SiN formed on said first layer of SiN; the first SiN layer having a first thickness and generating tensile stress in the structure and the second SiN layer having a second thickness and generating compressive stress in the structure.

摘要翻译： 一种包括III-N材料层并且所述层的至少一部分被钝化层覆盖的半导体结构，其中所述钝化层包括在所述III-N材料的所述至少一部分上形成的第一SiN层 层和形成在所述第一SiN层上的第二SiN层; 所述第一SiN层具有第一厚度并且在所述结构中产生拉伸应力，并且所述第二SiN层具有第二厚度并在所述结构中产生压应力。

公开(公告)号：EP3053196A1

公开(公告)日：2016-08-10

申请号：EP14847483.6

申请日：2014-09-16

申请人： HRL Laboratories, LLC

发明人： CHU, Rongming ,  CHEN, Mary Y. ,  LI, Zijian "Ray" ,  BOUTROS, Karim S. ,  CHEN, Xu ,  BROWN, David F. ,  WILLIAMS, Adam J.

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7827 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66666 ,  H01L29/7783 ,  H01L29/7786

摘要： A field-effect transistor (FET) includes a plurality of semiconductor layers, a source electrode and a drain electrode contacting one of the semiconductor layers, a first dielectric layer on a portion of a top semiconductor surface between the source and drain electrodes, a first trench extending through the first dielectric layer and having a bottom located on a top surface or within one of the semiconductor layers, a second dielectric layer lining the first trench and covering a portion of the first dielectric layer, a third dielectric layer over the semiconductor layers, the first dielectric layer, and the second dielectric layer, a second trench extending through the third dielectric layer and having a bottom located in the first trench on the second dielectric layer and extending over a portion of the second dielectric, and a gate electrode filling the second trench.

公开(公告)号：EP2737537A1

公开(公告)日：2014-06-04

申请号：EP12819630.0

申请日：2012-06-19

申请人： HRL Laboratories, LLC

发明人： CHU, Rongming ,  BROWN, David F. ,  CHEN, Xu ,  WILLIAMS, Adam J. ,  BOUTROS, Karim S.

IPC分类号： H01L29/772 ,  H01L21/335

摘要： A field effect transistor (FET) includes a III-Nitride channel layer, a III-Nitride barrier layer on the channel layer, wherein the barrier layer has an energy bandgap greater than the channel layer, a source electrode electrically coupled to one of the III-Nitride layers, a drain electrode electrically coupled to one of the III-Nitride layers, a gate insulator layer stack for electrically insulating a gate electrode from the barrier layer and the channel layer, the gate insulator layer stack including an insulator layer, such as SiN, and an AlN layer, the gate electrode in a region between the source electrode and the drain electrode and in contact with the insulator layer, and wherein the AlN layer is in contact with one of the III-Nitride layers.