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13 条记录 (耗时 0.01 秒)

    Self-test of over-current fault detection
    2.
    发明公开
    Self-test of over-current fault detection 审中-公开
    Selbsttest einerÜberspannungsfehlererkennung

    公开(公告)号：EP2690784A1

    公开(公告)日：2014-01-29

    申请号：EP13176489.6

    申请日：2013-07-15

    申请人： Hamilton Sundstrand Corporation

    发明人： Saloio, James ,  Gosse, James A.

    IPC分类号： H03K17/082 ,  G01R31/317 ,  H02H3/04 ,  H02H3/08

    CPC分类号： H02H3/044 ,  H02H3/08 ,  H03K17/0822

    摘要： A system for testing over-current fault detection includes first switch 14 to connect a voltage to a load and a capacitor 20;a first monitor circuit 38 that monitors a current from the first switch to the load; a second monitor circuit 200 that monitors a voltage across the capacitor; and a microcontroller 12 configured to control a state of the first switch to connect voltage to the load and verifies over-current detection based upon current generated during charging of the capacitor. The microcontroller an over-current fault condition based upon input from the first monitor circuit and detects a short-circuit fault condition based upon input from the second monitor circuit during test of the first monitor circuit.

    摘要翻译： 用于测试过电流故障检测的系统包括将电压连接到负载和电容器20的第一开关14;监视从第一开关到负载的电流的第一监视电路38; 监视电容器两端的电压的第二监视电路200; 以及微控制器12，被配置为控制第一开关的状态以将电压连接到负载，并且基于在电容器的充电期间产生的电流来验证过电流检测。 微控制器基于来自第一监视器电路的输入的过电流故障状况，并且在第一监视电路的测试期间基于来自第二监视电路的输入来检测短路故障状况。

    RAM single event upset (SEU) method to correct errors
    4.
    发明授权
    RAM single event upset (SEU) method to correct errors 有权
    RAM SEU方法用于纠错

    公开(公告)号：EP2437172B1

    公开(公告)日：2013-08-21

    申请号：EP11178698.4

    申请日：2011-08-24

    申请人： Hamilton Sundstrand Corporation

    发明人： Cox, Robert E. ,  Gosse, James A. ,  Sendlein, Kimberly K. ,  Harman, David S.

    IPC分类号： G06F11/16 ,  G06F11/10

    CPC分类号： G06F11/1048 ,  G06F11/167

    摘要： An error detection and correction (EDAC) circuit (20) mitigates the effect of single event upsets (SEU) events in a redundant memory system (10). The EDAC circuit (20) includes a first input for receiving first data and parity information stored by a first memory device (16) and a second input for receiving second data and parity information stored by a second memory device (18). First parity check logic (50a) calculates parity for the received first data and parity information. Second parity check logic (50b) calculates parity for the received second data and parity information. Bit comparison logic detects (52) differences between the first data and the second data, and between the first parity information and the second parity information. Based on the parity check calculated for the first and second data, and the bit comparison, data select logic (54) selects either the first data or the second data for provision to a data bus (38).

    Self-test of over-current fault detection
    5.
    发明授权
    Self-test of over-current fault detection 审中-公开

    公开(公告)号：EP2690784B1

    公开(公告)日：2018-12-26

    申请号：EP13176489.6

    申请日：2013-07-15

    申请人： Hamilton Sundstrand Corporation

    发明人： Saloio, James ,  Gosse, James A.

    IPC分类号： H03K17/082 ,  G01R31/317 ,  H02H3/04 ,  H02H3/08

    CPC分类号： H02H3/044 ,  H02H3/08 ,  H03K17/0822

    摘要： A system for testing over-current fault detection includes first switch 14 to connect a voltage to a load and a capacitor 20;a first monitor circuit 38 that monitors a current from the first switch to the load; a second monitor circuit 200 that monitors a voltage across the capacitor; and a microcontroller 12 configured to control a state of the first switch to connect voltage to the load and verifies over-current detection based upon current generated during charging of the capacitor. The microcontroller an over-current fault condition based upon input from the first monitor circuit and detects a short-circuit fault condition based upon input from the second monitor circuit during test of the first monitor circuit.

    RAM single event upset (SEU) method to correct errors
    8.
    发明公开
    RAM single event upset (SEU) method to correct errors 有权
    RAM-SEU-Verfahren zur Fehlerberichtigung

    公开(公告)号：EP2437172A1

    公开(公告)日：2012-04-04

    申请号：EP11178698.4

    申请日：2011-08-24

    申请人： Hamilton Sundstrand Corporation

    发明人： Cox, Robert E. ,  Gosse, James A. ,  Sendlein, Kimberly K. ,  Harman, David S.

    IPC分类号： G06F11/16 ,  G06F11/10

    CPC分类号： G06F11/1048 ,  G06F11/167

    摘要： An error detection and correction (EDAC) circuit (20) mitigates the effect of single event upsets (SEU) events in a redundant memory system (10). The EDAC circuit (20) includes a first input for receiving first data and parity information stored by a first memory device (16) and a second input for receiving second data and parity information stored by a second memory device (18). First parity check logic (50a) calculates parity for the received first data and parity information. Second parity check logic (50b) calculates parity for the received second data and parity information. Bit comparison logic detects (52) differences between the first data and the second data, and between the first parity information and the second parity information. Based on the parity check calculated for the first and second data, and the bit comparison, data select logic (54) selects either the first data or the second data for provision to a data bus (38).

    摘要翻译： 错误检测和校正（EDAC）电路（20）减轻冗余存储器系统（10）中的单事件故障（SEU）事件的影响。 EDAC电路（20）包括用于接收由第一存储器设备（16）存储的第一数据和奇偶校验信息的第一输入端和用于接收第二存储器件（18）存储的第二数据和奇偶校验信息的第二输入端。 第一奇偶校验逻辑（50a）计算接收的第一数据和奇偶校验信息的奇偶校验。 第二奇偶校验逻辑（50b）计算接收到的第二数据和奇偶校验信息的奇偶校验。 位比较逻辑检测（52）第一数据和第二数据之间以及第一奇偶信息和第二奇偶校验信息之间的差异。 基于针对第一和第二数据计算的奇偶校验和位比较，数据选择逻辑（54）选择第一数据或第二数据以提供给数据总线（38）。

    Detecting a relative shaft position on geared shafts
    10.
    发明公开
    Detecting a relative shaft position on geared shafts 有权
    数字电路和方法，用于检测在轴的花键轴的相对位置

    公开(公告)号：EP2660565A2

    公开(公告)日：2013-11-06

    申请号：EP13157506.0

    申请日：2013-03-01

    申请人： Hamilton Sundstrand Corporation

    发明人： Hess, Gary L. ,  Gosse, James A. ,  Leblanc, Paul J ,  Saloio, James

    IPC分类号： G01D5/14 ,  G01D5/347

    CPC分类号： B23F15/04 ,  B23F17/001 ,  G01D5/145 ,  G01D5/245 ,  G01D5/2451 ,  Y10T74/19642

    摘要： A system (100) for determining a relative position of a secondary gear (12) includes a gear assembly (10) including a phonic wheel (13) fixed to a primary gear (11) and a secondary gear (12) rotatably engaged to the first gear, a sensor (20) configured to output a signal upon detecting a tooth (14) of the phonic wheel, and a digital logic circuit (30) configured to detect a revolution of the phonic wheel, to generate a primary gear tooth pulse at intervals corresponding to intervals of teeth (15) of the primary gear based on the detected revolution of the phonic wheel, and to generate a secondary gear revolution signal at an interval corresponding to a revolution of the secondary gear (12) based on the primary gear tooth pulse.

    摘要翻译： 一种用于确定性采矿次级齿轮的相对位置（12）的系统（100）包括一齿轮组件（10），包括固定到一个主齿轮（11）和次级齿轮（12），一个音轮（13）可旋转地接合到所述 第一齿轮，在检测到发音轮的齿（14）被配置为输出的信号的传感器（20），和配置成检测所述音轮的旋转的数字逻辑电路（30），以产生一个初级齿轮齿脉冲 间隔对应于基于所述音轮的检测到的转速的初级齿轮的齿（15）的间隔，并生成在在间隔对应于副齿轮的转速的次级齿轮旋转信号（12）基于主 齿轮齿脉冲。