公开(公告)号：EP2686774A1

公开(公告)日：2014-01-22

申请号：EP11860733.2

申请日：2011-03-14

申请人： Hewlett-Packard Development Company, L.P.

发明人： UDIPI, Aniruddha Nagendran ,  MURALIMANOHAR, Naveen ,  JOUPPI, Norman Paul ,  BALASUBRAMONIAN, Rajeev ,  DAVIS, Alan Lynn

IPC分类号： G06F13/16 ,  G06F12/00

CPC分类号： G06F13/3625 ,  G06F13/1605 ,  G06F13/1689

摘要： The present disclosure provides a method for processing memory access operations. The method includes determining a fixed response time based, at least in part, on a total memory latency of a memory module. The method also includes identifying an available time slot for receiving return data from the memory module over a data bus, wherein the time difference between a current clock cycle and the available time slot is greater than or equal to the fixed response time. The method also includes creating a first slot reservation by reserving the available time slot. The method also includes issuing a read request to the memory module over the data bus, wherein the read request is issued at a clock cycle determined by subtracting the fixed response time from a time of the first slot reservation.

公开(公告)号：EP2856471A1

公开(公告)日：2015-04-08

申请号：EP12877868.5

申请日：2012-05-31

申请人： Hewlett-Packard Development Company, L.P.

发明人： UDIPI, Aniruddha Nagendran ,  MURALIMANOHAR, Naveen ,  JOUPPI, Norman Paul ,  DAVIS, Alan Lynn ,  BALASUBRAMONIAN, Rajeev

IPC分类号： G11C29/42

CPC分类号： G06F11/1064 ,  G06F11/1012 ,  G06F11/1044 ,  G06F11/108 ,  G11C2029/0411

摘要： A system may use local error detection (LED) and global error correction (GEC) information to check data fidelity and correct an error. The LED may be calculated per cache line segment of data associated with a rank of a memory. Data fidelity may be checked in response to a memory read operation, based on the LED information, to identify a presence of an error and the location of the error among cache line segments of the rank. The cache line segment having the error may be corrected based on the GEC, in response to identifying the error.

公开(公告)号：EP2529374A2

公开(公告)日：2012-12-05

申请号：EP11737663.2

申请日：2011-01-27

申请人： Hewlett Packard Development Company, L.P. ,  University of Utah Research Foundation

发明人： MURALIMANOHAR, Naveen ,  UDIPI, Aniruddha Nagendran ,  CHATTERJEE, Niladrish ,  BALASUBRAMONIAN, Rajeev ,  DAVIS, Alan Lynn ,  JOUPPI, Norman Paul

IPC分类号： G11C11/4063 ,  G11C7/10 ,  G06F12/00

CPC分类号： G06F3/0625 ,  G06F3/0634 ,  G06F3/0658 ,  G06F3/0673 ,  G06F11/1088 ,  G06F12/0802 ,  G06F12/0893 ,  G06F2212/1028 ,  G06F2212/3042 ,  G06F2212/305 ,  G11C5/04 ,  G11C7/10 ,  G11C8/12 ,  G11C11/4082 ,  Y02D10/13

摘要： An example apparatus includes a row address register to store a row address corresponding to a row in a memory array. The example apparatus also includes a row decoder coupled to the row address register to assert a signal on a wordline of the row after the memory receives a column address. In addition, the example apparatus includes a column decoder to selectively activate a portion of the row based on the column address and the signal asserted on the wordline.